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Searched refs:dsi_dcs_write_seq (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/panel/
A Dpanel-leadtek-ltk050h3146w.c264 dsi_dcs_write_seq(dsi, 0xdf, 0x93, 0x65, 0xf8); in ltk050h3146w_init_sequence()
267 dsi_dcs_write_seq(dsi, 0xb2, 0x00, 0xb5); in ltk050h3146w_init_sequence()
268 dsi_dcs_write_seq(dsi, 0xb3, 0x00, 0xb5); in ltk050h3146w_init_sequence()
274 dsi_dcs_write_seq(dsi, 0xbc, 0x0f, 0x04); in ltk050h3146w_init_sequence()
275 dsi_dcs_write_seq(dsi, 0xbe, 0x1e, 0xf2); in ltk050h3146w_init_sequence()
276 dsi_dcs_write_seq(dsi, 0xc0, 0x26, 0x03); in ltk050h3146w_init_sequence()
277 dsi_dcs_write_seq(dsi, 0xc1, 0x00, 0x12); in ltk050h3146w_init_sequence()
306 dsi_dcs_write_seq(dsi, 0xde, 0x02); in ltk050h3146w_init_sequence()
307 dsi_dcs_write_seq(dsi, 0xb2, 0x32, 0x1c); in ltk050h3146w_init_sequence()
309 dsi_dcs_write_seq(dsi, 0xc1, 0x11); in ltk050h3146w_init_sequence()
[all …]
A Dpanel-sitronix-st7703.c185 dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, in xbd599_init_sequence()
204 dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, in xbd599_init_sequence()
215 dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, in xbd599_init_sequence()
239 dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, in xbd599_init_sequence()
249 dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, in xbd599_init_sequence()
272 dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, in xbd599_init_sequence()
290 dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, in xbd599_init_sequence()
295 dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, in xbd599_init_sequence()
303 dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, in xbd599_init_sequence()
314 dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, in xbd599_init_sequence()
[all …]
A Dpanel-elida-kd35t133.c54 #define dsi_dcs_write_seq(dsi, cmd, seq...) do { \ macro
71 dsi_dcs_write_seq(dsi, KD35T133_CMD_POSITIVEGAMMA, in kd35t133_init_sequence()
74 dsi_dcs_write_seq(dsi, KD35T133_CMD_NEGATIVEGAMMA, in kd35t133_init_sequence()
78 dsi_dcs_write_seq(dsi, KD35T133_CMD_POWERCONTROL2, 0x41); in kd35t133_init_sequence()
80 dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x48); in kd35t133_init_sequence()
81 dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PIXEL_FORMAT, 0x55); in kd35t133_init_sequence()
82 dsi_dcs_write_seq(dsi, KD35T133_CMD_INTERFACEMODECTRL, 0x00); in kd35t133_init_sequence()
83 dsi_dcs_write_seq(dsi, KD35T133_CMD_FRAMERATECTRL, 0xa0); in kd35t133_init_sequence()
85 dsi_dcs_write_seq(dsi, KD35T133_CMD_DISPLAYFUNCTIONCTRL, in kd35t133_init_sequence()
87 dsi_dcs_write_seq(dsi, KD35T133_CMD_SETIMAGEFUNCTION, 0x00); in kd35t133_init_sequence()
[all …]
A Dpanel-samsung-s6e88a0-ams452ef01.c31 #define dsi_dcs_write_seq(dsi, seq...) do { \ macro
57 dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands in s6e88a0_ams452ef01_on()
58 dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity in s6e88a0_ams452ef01_on()
68 dsi_dcs_write_seq(dsi, 0xca, in s6e88a0_ams452ef01_on()
80 dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); in s6e88a0_ams452ef01_on()
81 dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage in s6e88a0_ams452ef01_on()
82 dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in s6e88a0_ams452ef01_on()
83 dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update in s6e88a0_ams452ef01_on()
84 dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands in s6e88a0_ams452ef01_on()
A Dpanel-samsung-sofef00.c37 #define dsi_dcs_write_seq(dsi, seq...) do { \ macro
70 dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
78 dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
79 dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
80 dsi_dcs_write_seq(dsi, 0xb0, 0x07); in sofef00_panel_on()
81 dsi_dcs_write_seq(dsi, 0xb6, 0x12); in sofef00_panel_on()
82 dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
83 dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20); in sofef00_panel_on()
84 dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in sofef00_panel_on()
A Dpanel-sharp-ls060t1sx01.c35 #define dsi_dcs_write_seq(dsi, seq...) ({ \ macro
59 ret = dsi_dcs_write_seq(dsi, 0xbb, 0x13); in sharp_ls060_on()
65 ret = dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START); in sharp_ls060_on()
A Dpanel-asus-z00t-tm5p5-n35596.c35 #define dsi_dcs_write_seq(dsi, seq...) do { \ macro
120 dsi_dcs_write_seq(dsi, 0x4f, 0x01); in tm5p5_nt35596_off()

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