| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_dwb.c | 46 static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb3_get_caps() argument
66 void dwb3_config_fc(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb3_config_fc() argument
91 bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb3_enable() argument
100 dwb3_config_fc(dwbc, params); in dwb3_enable()
119 bool dwb3_disable(struct dwbc *dwbc) in dwb3_disable() argument
133 bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb3_update() argument
171 bool dwb3_is_enabled(struct dwbc *dwbc) in dwb3_is_enabled() argument
183 void dwb3_set_stereo(struct dwbc *dwbc, in dwb3_set_stereo() argument
198 void dwb3_set_new_content(struct dwbc *dwbc, in dwb3_set_new_content() argument
206 void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb3_set_denorm() argument
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| A D | dcn30_dwb_cm.c | 270 struct dwbc *dwbc, in dwb3_ogam_set_input_transfer_func() argument
273 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_ogam_set_input_transfer_func()
298 struct dwbc *dwbc, in dwb3_program_gamut_remap() argument
303 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_program_gamut_remap()
353 struct dwbc *dwbc, in dwb3_set_gamut_remap() argument
356 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_set_gamut_remap()
362 dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS); in dwb3_set_gamut_remap()
376 dwb3_program_gamut_remap(dwbc, arr_reg_val, in dwb3_set_gamut_remap()
379 dwb3_program_gamut_remap(dwbc, arr_reg_val, in dwb3_set_gamut_remap()
386 struct dwbc *dwbc, in dwb3_program_hdr_mult() argument
[all …]
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| A D | dcn30_dwb.h | 876 struct dwbc base;
889 bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);
891 bool dwb3_disable(struct dwbc *dwbc);
893 bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);
895 bool dwb3_is_enabled(struct dwbc *dwbc);
897 void dwb3_set_stereo(struct dwbc *dwbc,
900 void dwb3_set_new_content(struct dwbc *dwbc,
903 void dwb3_config_fc(struct dwbc *dwbc,
909 struct dwbc *dwbc,
913 struct dwbc *dwbc,
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| A D | dcn30_hwseq.c | 247 struct dwbc *dwb; in dcn30_update_writeback()
248 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
264 struct dwbc *dwb; in dcn30_mmhubbub_warmup()
270 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
299 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
322 struct dwbc *dwb; in dcn30_enable_writeback()
326 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_enable_writeback()
351 struct dwbc *dwb; in dcn30_disable_writeback()
355 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dcn30_disable_writeback()
374 struct dwbc *dwb; in dcn30_program_all_writeback_pipes_in_tree()
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| A D | dcn30_resource.c | 1284 if (pool->base.dwbc[i] != NULL) { in dcn30_resource_destruct()
1285 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn30_resource_destruct()
1286 pool->base.dwbc[i] = NULL; in dcn30_resource_destruct()
1376 pool->dwbc[i] = &dwbc30->base; in dcn30_dwbc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | dwb.h | 181 struct dwbc *dwbc, argument
185 struct dwbc *dwbc,
191 struct dwbc *dwbc,
195 struct dwbc *dwbc);
198 struct dwbc *dwbc,
202 struct dwbc *dwbc,
207 struct dwbc *dwbc,
214 struct dwbc *dwbc,
219 struct dwbc *dwbc,
230 struct dwbc *dwbc,
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dwb.c | 50 static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb2_get_caps() argument
72 void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_config_dwb_cnv() argument
99 static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_enable() argument
124 dwb2_set_scaler(dwbc, params); in dwb2_enable()
135 bool dwb2_disable(struct dwbc *dwbc) in dwb2_disable() argument
158 static bool dwb2_update(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_update() argument
198 bool dwb2_is_enabled(struct dwbc *dwbc) in dwb2_is_enabled() argument
210 void dwb2_set_stereo(struct dwbc *dwbc, in dwb2_set_stereo() argument
226 void dwb2_set_new_content(struct dwbc *dwbc, in dwb2_set_new_content() argument
235 static void dwb2_set_warmup(struct dwbc *dwbc, in dwb2_set_warmup() argument
[all …]
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| A D | dcn20_dwb.h | 416 struct dwbc base;
429 bool dwb2_disable(struct dwbc *dwbc);
431 bool dwb2_is_enabled(struct dwbc *dwbc);
433 void dwb2_set_stereo(struct dwbc *dwbc,
436 void dwb2_set_new_content(struct dwbc *dwbc,
439 void dwb2_config_dwb_cnv(struct dwbc *dwbc,
442 void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
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| A D | dcn20_hwseq.c | 1911 struct dwbc *dwb; in dcn20_enable_writeback()
1917 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
1937 struct dwbc *dwb; in dcn20_disable_writeback()
1941 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dcn20_disable_writeback()
2569 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn20_fpga_init_hw()
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| A D | dcn20_resource.c | 1530 if (pool->base.dwbc[i] != NULL) { in dcn20_resource_destruct()
1531 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); in dcn20_resource_destruct()
1532 pool->base.dwbc[i] = NULL; in dcn20_resource_destruct()
3416 pool->dwbc[i] = &dwbc20->base; in dcn20_dwbc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_dwb.c | 47 static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb1_get_caps() argument
66 static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb1_enable() argument
68 struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); in dwb1_enable()
71 dwbc->funcs->disable(dwbc); in dwb1_enable()
83 static bool dwb1_disable(struct dwbc *dwbc) in dwb1_disable() argument
85 struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); in dwb1_disable()
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| A D | dcn10_dwb.h | 256 struct dwbc base;
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 227 struct dwbc *dwbc[MAX_DWB_PIPES]; member
388 struct dwbc *dwbc; member
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_stream.c | 437 struct dwbc *dwb; in dc_stream_add_writeback()
456 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
476 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
487 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 1138 if (pool->base.dwbc[i] != NULL) { in dcn301_destruct()
1139 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn301_destruct()
1140 pool->base.dwbc[i] = NULL; in dcn301_destruct()
1224 pool->dwbc[i] = &dwbc30->base; in dcn301_dwbc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn302/ |
| A D | dcn302_resource.c | 857 pool->dwbc[i] = &dwbc30->base; in dcn302_dwbc_create()
1207 if (pool->dwbc[i] != NULL) { in dcn302_resource_destruct()
1208 kfree(TO_DCN30_DWBC(pool->dwbc[i])); in dcn302_resource_destruct()
1209 pool->dwbc[i] = NULL; in dcn302_resource_destruct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
| A D | dcn303_resource.c | 799 pool->dwbc[i] = &dwbc30->base; in dcn303_dwbc_create()
1133 if (pool->dwbc[i] != NULL) { in dcn303_resource_destruct()
1134 kfree(TO_DCN30_DWBC(pool->dwbc[i])); in dcn303_resource_destruct()
1135 pool->dwbc[i] = NULL; in dcn303_resource_destruct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.c | 1606 if (pool->base.dwbc[i] != NULL) { in dcn31_resource_destruct()
1607 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn31_resource_destruct()
1608 pool->base.dwbc[i] = NULL; in dcn31_resource_destruct()
1695 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 986 if (pool->base.dwbc[i] != NULL) { in dcn21_resource_destruct()
987 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); in dcn21_resource_destruct()
988 pool->base.dwbc[i] = NULL; in dcn21_resource_destruct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_hwseq.c | 341 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn201_init_hw()
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