| /linux/drivers/gpu/drm/radeon/ |
| A D | r600_dpm.c | 1202 rdev->pm.dpm.dyn_state.ppm_table = in r600_parse_extended_power_table()
1204 if (!rdev->pm.dpm.dyn_state.ppm_table) { in r600_parse_extended_power_table()
1219 rdev->pm.dpm.dyn_state.ppm_table->apu_tdp = in r600_parse_extended_power_table()
1221 rdev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = in r600_parse_extended_power_table()
1225 rdev->pm.dpm.dyn_state.ppm_table->tj_max = in r600_parse_extended_power_table()
1260 rdev->pm.dpm.dyn_state.cac_tdp_table = in r600_parse_extended_power_table()
1262 if (!rdev->pm.dpm.dyn_state.cac_tdp_table) { in r600_parse_extended_power_table()
1300 struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state; in r600_free_extended_power_table() local
1306 kfree(dyn_state->cac_leakage_table.entries); in r600_free_extended_power_table()
1308 kfree(dyn_state->ppm_table); in r600_free_extended_power_table()
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| A D | btc_dpm.c | 1284 rdev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
1290 rdev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
2698 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in btc_dpm_init()
2699 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in btc_dpm_init()
2700 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900; in btc_dpm_init()
2703 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in btc_dpm_init()
2704 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in btc_dpm_init()
2707 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in btc_dpm_init()
2709 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 10000; in btc_dpm_init()
2714 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in btc_dpm_init()
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| A D | ci_dpm.c | 395 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
412 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_parameters_in_dpm_table()
647 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_enable_power_containment()
721 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_power_control_set_level()
1599 rdev->pm.dpm.dyn_state.cac_tdp_table;
3408 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3410 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
3412 &rdev->pm.dpm.dyn_state.cac_leakage_table; in ci_setup_default_dpm_tables()
5768 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in ci_dpm_init()
5769 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in ci_dpm_init()
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| A D | si_dpm.c | 2517 &rdev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
3956 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
4149 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4164 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
7038 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
7039 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
7040 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
7041 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
7043 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
7051 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
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| A D | ni_dpm.c | 1012 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ni_patch_dependency_tables_based_on_leakage()
1015 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ni_patch_dependency_tables_based_on_leakage()
1346 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries && in ni_get_std_voltage_value()
3099 &rdev->pm.dpm.dyn_state.cac_leakage_table; in ni_init_simplified_leakage_table()
4198 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3; in ni_dpm_init()
4199 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in ni_dpm_init()
4200 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900; in ni_dpm_init()
4203 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ni_dpm_init()
4205 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500; in ni_dpm_init()
4264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ni_dpm_init()
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| A D | kv_dpm.c | 399 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
421 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
562 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
923 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1533 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
1905 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
1946 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
1949 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_apply_state_adjust_rules()
2083 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_calculate_nbps_level_settings()
2150 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
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| A D | rv770_dpm.c | 2261 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in rv7xx_parse_pplib_clock_info()
2262 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in rv7xx_parse_pplib_clock_info()
2263 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in rv7xx_parse_pplib_clock_info()
2264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in rv7xx_parse_pplib_clock_info()
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| /linux/drivers/gpu/drm/amd/pm/ |
| A D | amdgpu_dpm.c | 615 adev->pm.dpm.dyn_state.ppm_table = in amdgpu_parse_extended_power_table()
617 if (!adev->pm.dpm.dyn_state.ppm_table) { in amdgpu_parse_extended_power_table()
632 adev->pm.dpm.dyn_state.ppm_table->apu_tdp = in amdgpu_parse_extended_power_table()
634 adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = in amdgpu_parse_extended_power_table()
638 adev->pm.dpm.dyn_state.ppm_table->tj_max = in amdgpu_parse_extended_power_table()
673 adev->pm.dpm.dyn_state.cac_tdp_table = in amdgpu_parse_extended_power_table()
675 if (!adev->pm.dpm.dyn_state.cac_tdp_table) { in amdgpu_parse_extended_power_table()
726 struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state; in amdgpu_free_extended_power_table() local
732 kfree(dyn_state->cac_leakage_table.entries); in amdgpu_free_extended_power_table()
734 kfree(dyn_state->ppm_table); in amdgpu_free_extended_power_table()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | processpptables.c | 1406 &hwmgr->dyn_state.cac_dtp_table, in init_clock_voltage_dependency()
1455 &hwmgr->dyn_state.valid_sclk_values, in init_clock_voltage_dependency()
1532 hwmgr->dyn_state.ppm_parameter_table = ptr; in get_platform_power_management_table()
1766 kfree(hwmgr->dyn_state.valid_mclk_values); in pp_tables_uninitialize()
1767 hwmgr->dyn_state.valid_mclk_values = NULL; in pp_tables_uninitialize()
1769 kfree(hwmgr->dyn_state.valid_sclk_values); in pp_tables_uninitialize()
1770 hwmgr->dyn_state.valid_sclk_values = NULL; in pp_tables_uninitialize()
1772 kfree(hwmgr->dyn_state.cac_leakage_table); in pp_tables_uninitialize()
1773 hwmgr->dyn_state.cac_leakage_table = NULL; in pp_tables_uninitialize()
1790 kfree(hwmgr->dyn_state.cac_dtp_table); in pp_tables_uninitialize()
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| A D | smu8_hwmgr.c | 104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
262 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_construct_max_power_limits_table()
444 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_upload_pptable_to_smu()
446 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk; in smu8_upload_pptable_to_smu()
558 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_init_sclk_limit()
687 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_update_sclk_limit()
1162 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_phm_unforce_dpm_levels()
1507 hwmgr->dyn_state.vddc_dep_on_dal_pwrl; in smu8_get_dal_power_level()
1509 &hwmgr->dyn_state.max_clock_voltage_on_ac; in smu8_get_dal_power_level()
1549 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_print_clock_levels()
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| A D | smu7_hwmgr.c | 338 hwmgr->dyn_state.mvdd_dependency_on_mclk); in smu7_construct_voltage_tables()
358 hwmgr->dyn_state.vddci_dependency_on_mclk); in smu7_construct_voltage_tables()
383 hwmgr->dyn_state.vddc_dependency_on_mclk); in smu7_construct_voltage_tables()
786 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_setup_dpm_tables_v0()
788 hwmgr->dyn_state.vddc_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
790 hwmgr->dyn_state.cac_leakage_table; in smu7_setup_dpm_tables_v0()
2828 …if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk… in smu7_set_private_data_based_on_pptable_v0()
2829 …hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entrie… in smu7_set_private_data_based_on_pptable_v0()
2836 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in smu7_hwmgr_backend_fini()
2837 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in smu7_hwmgr_backend_fini()
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| A D | hwmgr.c | 245 if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) || in hwmgr_hw_init()
246 (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0)) in hwmgr_hw_init()
247 hwmgr->dyn_state.max_clock_voltage_on_dc = in hwmgr_hw_init()
248 hwmgr->dyn_state.max_clock_voltage_on_ac; in hwmgr_hw_init()
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| A D | process_pptables_v1_0.c | 582 hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL); in get_cac_tdp_table()
584 if (NULL == hwmgr->dyn_state.cac_dtp_table) { in get_cac_tdp_table()
848 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_clock_voltage_dependency()
850 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_clock_voltage_dependency()
852 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_clock_voltage_dependency()
854 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_clock_voltage_dependency()
1219 kfree(hwmgr->dyn_state.cac_dtp_table); in pp_tables_v1_0_uninitialize()
1220 hwmgr->dyn_state.cac_dtp_table = NULL; in pp_tables_v1_0_uninitialize()
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| A D | vega10_processpptables.c | 993 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_powerplay_extended_tables()
995 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_powerplay_extended_tables()
997 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_powerplay_extended_tables()
999 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_powerplay_extended_tables()
1232 kfree(hwmgr->dyn_state.cac_dtp_table); in vega10_pp_tables_uninitialize()
1233 hwmgr->dyn_state.cac_dtp_table = NULL; in vega10_pp_tables_uninitialize()
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| A D | smu10_hwmgr.c | 161 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in smu10_init_dynamic_state_adjustment_rule_settings()
177 &hwmgr->dyn_state.max_clock_voltage_on_ac); in smu10_get_system_info_data()
605 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in smu10_hwmgr_backend_fini()
606 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in smu10_hwmgr_backend_fini()
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| A D | ppatomctrl.c | 1162 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) { in atomctrl_get_voltage_evv()
1163 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) { in atomctrl_get_voltage_evv()
1169 if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) { in atomctrl_get_voltage_evv()
1178 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk); in atomctrl_get_voltage_evv()
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| A D | vega10_hwmgr.c | 795 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = in vega10_set_private_data_based_on_pptable()
797 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = in vega10_set_private_data_based_on_pptable()
799 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = in vega10_set_private_data_based_on_pptable()
801 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = in vega10_set_private_data_based_on_pptable()
809 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in vega10_hwmgr_backend_fini()
810 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in vega10_hwmgr_backend_fini()
3266 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : in vega10_apply_state_adjust_rules()
3267 &(hwmgr->dyn_state.max_clock_voltage_on_dc); in vega10_apply_state_adjust_rules()
3296 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); in vega10_apply_state_adjust_rules()
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| A D | smu7_powertune.c | 1163 cac_table = hwmgr->dyn_state.cac_dtp_table; in smu7_enable_power_containment()
1253 cac_table = hwmgr->dyn_state.cac_dtp_table; in smu7_power_control_set_level()
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| A D | smu_helper.c | 529 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in phm_initializa_dynamic_state_adjustment_rule_settings()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| A D | ci_smumgr.c | 418 hwmgr->dyn_state.vddc_dependency_on_sclk, clock, in ci_populate_single_graphic_level()
430 hwmgr->dyn_state.vddc_phase_shed_limits_table, in ci_populate_single_graphic_level()
588 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in ci_populate_bapm_vddc_vid_sidd()
776 if (NULL == hwmgr->dyn_state.cac_leakage_table) { in ci_get_std_voltage_value_sidd()
789 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in ci_get_std_voltage_value_sidd()
790 …*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->c… in ci_get_std_voltage_value_sidd()
805 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in ci_get_std_voltage_value_sidd()
1195 hwmgr->dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
1204 hwmgr->dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
2866 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc; in ci_update_uvd_smc_table()
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| A D | iceland_smumgr.c | 396 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in iceland_populate_bapm_vddc_vid_sidd()
400 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in iceland_populate_bapm_vddc_vid_sidd()
544 if (NULL == hwmgr->dyn_state.cac_leakage_table) { in iceland_get_std_voltage_value_sidd()
562 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in iceland_get_std_voltage_value_sidd()
563 …*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->c… in iceland_get_std_voltage_value_sidd()
582 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in iceland_get_std_voltage_value_sidd()
583 …*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->c… in iceland_get_std_voltage_value_sidd()
902 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, in iceland_populate_single_graphic_level()
913 hwmgr->dyn_state.vddc_phase_shed_limits_table, in iceland_populate_single_graphic_level()
1240 if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) { in iceland_populate_single_memory_level()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/ |
| A D | si_dpm.c | 2617 &adev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
3284 adev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
3290 adev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
4611 …adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4626 …adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
7445 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
7446 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
7447 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
7448 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
7458 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
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| A D | kv_dpm.c | 76 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
98 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
803 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
1164 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1776 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
2172 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2213 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2216 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_apply_state_adjust_rules()
2350 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_calculate_nbps_level_settings()
2417 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
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| /linux/drivers/gpu/drm/amd/pm/inc/ |
| A D | amdgpu_dpm.h | 399 struct amdgpu_dpm_dynamic_state dyn_state; member
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| A D | hwmgr.h | 781 struct phm_dynamic_state_info dyn_state; member
|