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Searched refs:enable_value (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/irq/dce80/
A Dirq_service_dce80.c98 .enable_value = {\
113 .enable_value = {\
128 .enable_value = {\
143 .enable_value = {\
159 .enable_value = {\
/linux/drivers/gpu/drm/amd/display/dc/irq/dce60/
A Dirq_service_dce60.c105 .enable_value = {\
120 .enable_value = {\
135 .enable_value = {\
150 .enable_value = {\
166 .enable_value = {\
/linux/drivers/gpu/drm/amd/display/dc/irq/dce110/
A Dirq_service_dce110.c95 .enable_value = {\
110 .enable_value = {\
124 .enable_value = {\
139 .enable_value = {\
155 .enable_value = {\
/linux/drivers/mmc/host/
A Dsdhci-of-aspeed.c58 u8 enable_value; member
135 reg |= desc->enable_value << __ffs(desc->enable_mask); in aspeed_sdc_set_phase_tap()
481 .enable_value = 1,
486 .enable_value = 3,
494 .enable_value = 1,
499 .enable_value = 3,
/linux/drivers/gpu/drm/amd/display/dc/irq/
A Dirq_service.h51 uint32_t enable_value[2]; member
A Dirq_service.c101 (info->enable_value[enable ? 0 : 1] & info->enable_mask); in dal_irq_service_set_generic()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
A Dirq_service_dcn30.c226 .enable_value = {\
240 .enable_value = {\
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
A Dirq_service_dcn302.c198 .enable_value = {\
217 .enable_value = {\
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
A Dirq_service_dcn31.c213 .enable_value = {\
227 .enable_value = {\
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
A Dirq_service_dcn21.c245 .enable_value = {\
259 .enable_value = {\
/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/
A Dirq_service_dce120.c109 .enable_value = {\
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/
A Dirq_service_dcn303.c113 .enable_value = {\
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/
A Dirq_service_dcn201.c164 .enable_value = {\
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/
A Dirq_service_dcn10.c207 .enable_value = {\
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/
A Dirq_service_dcn20.c234 .enable_value = {\

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