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Searched refs:feature_mask (Results 1 – 25 of 46) sorted by relevance

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/linux/drivers/gpu/drm/amd/pm/swsmu/
A Dsmu_cmn.c533 uint32_t *feature_mask, in smu_cmn_get_enabled_mask() argument
540 if (!feature_mask || num < 2) in smu_cmn_get_enabled_mask()
563 uint32_t *feature_mask, in smu_cmn_get_enabled_32_bits_mask() argument
571 if (!feature_mask || num < 2) in smu_cmn_get_enabled_32_bits_mask()
613 uint64_t feature_mask, in smu_cmn_feature_update_enable_state() argument
696 uint32_t feature_mask[2] = { 0 }; in smu_cmn_get_pp_feature_mask() local
705 feature_mask, in smu_cmn_get_pp_feature_mask()
711 feature_mask, in smu_cmn_get_pp_feature_mask()
718 feature_mask[1], feature_mask[0]); in smu_cmn_get_pp_feature_mask()
760 feature_mask, in smu_cmn_set_pp_feature_mask()
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A Dsmu_cmn.h57 uint32_t *feature_mask,
61 uint32_t *feature_mask,
69 uint64_t feature_mask,
A Dsmu_internal.h72 …e smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0,… argument
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dhwmgr.c102 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
113 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
118 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
123 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
131 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; in hwmgr_early_init()
144 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
149 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
160 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
170 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
443 if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK) in hwmgr_set_user_specify_caps()
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A Dvega10_hwmgr.c142 hwmgr->feature_mask & PP_ULV_MASK ? true : false; in vega10_set_default_registry_data()
154 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; in vega10_set_default_registry_data()
2896 uint32_t i, feature_mask = 0; in vega10_stop_dpm() local
2912 feature_mask |= data->smu_features[i]. in vega10_stop_dpm()
2935 uint32_t i, feature_mask = 0; in vega10_start_dpm() local
2941 feature_mask |= data->smu_features[i]. in vega10_start_dpm()
2950 true, feature_mask)) { in vega10_start_dpm()
2953 feature_mask) in vega10_start_dpm()
5473 uint32_t feature_mask = 0; in vega10_disable_power_features_for_compute_performance() local
5499 if (feature_mask) in vega10_disable_power_features_for_compute_performance()
[all …]
A Dvega20_hwmgr.c104 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK)) in vega20_set_default_registry_data()
107 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK)) in vega20_set_default_registry_data()
110 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK)) in vega20_set_default_registry_data()
113 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK)) in vega20_set_default_registry_data()
119 if (!(hwmgr->feature_mask & PP_ULV_MASK)) in vega20_set_default_registry_data()
1835 (feature_mask & FEATURE_DPM_UCLK_MASK)) { in vega20_upload_dpm_min_level()
1846 (feature_mask & FEATURE_DPM_UVD_MASK)) { in vega20_upload_dpm_min_level()
1867 (feature_mask & FEATURE_DPM_VCE_MASK)) { in vega20_upload_dpm_min_level()
1891 (feature_mask & FEATURE_DPM_FCLK_MASK)) { in vega20_upload_dpm_min_level()
1949 (feature_mask & FEATURE_DPM_UVD_MASK)) { in vega20_upload_dpm_max_level()
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/linux/drivers/thermal/intel/int340x_thermal/
A Dprocessor_thermal_device.c401 kernel_ulong_t feature_mask) in proc_thermal_mmio_add() argument
405 proc_priv->mmio_feature_mask = feature_mask; in proc_thermal_mmio_add()
407 if (feature_mask) { in proc_thermal_mmio_add()
413 if (feature_mask & PROC_THERMAL_FEATURE_RAPL) { in proc_thermal_mmio_add()
421 if (feature_mask & PROC_THERMAL_FEATURE_FIVR || in proc_thermal_mmio_add()
422 feature_mask & PROC_THERMAL_FEATURE_DVFS) { in proc_thermal_mmio_add()
430 if (feature_mask & PROC_THERMAL_FEATURE_MBOX) { in proc_thermal_mmio_add()
A Dprocessor_thermal_device.h90 kernel_ulong_t feature_mask);
/linux/arch/arm64/kernel/
A Dalternative.c137 unsigned long *feature_mask) in __apply_alternatives() argument
146 if (!test_bit(alt->cpufeature, feature_mask)) in __apply_alternatives()
189 feature_mask, ARM64_NCAPS); in __apply_alternatives()
/linux/drivers/mfd/
A Dkempld-core.c67 pld->feature_mask = kempld_read16(pld, KEMPLD_FEATURE); in kempld_get_info_generic()
69 pld->feature_mask = 0; in kempld_get_info_generic()
97 if (pld->feature_mask & KEMPLD_FEATURE_BIT_I2C) in kempld_register_cells_generic()
100 if (pld->feature_mask & KEMPLD_FEATURE_BIT_WATCHDOG) in kempld_register_cells_generic()
103 if (pld->feature_mask & KEMPLD_FEATURE_BIT_GPIO) in kempld_register_cells_generic()
106 if (pld->feature_mask & KEMPLD_FEATURE_MASK_UART) in kempld_register_cells_generic()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dyellow_carp_ppt.c200 uint32_t feature_mask[2]; in yellow_carp_system_features_control() local
212 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); in yellow_carp_system_features_control()
216 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, in yellow_carp_system_features_control()
218 bitmap_copy(feature->supported, (unsigned long *)&feature_mask, in yellow_carp_system_features_control()
258 uint32_t feature_mask[2]; in yellow_carp_is_dpm_running() local
261 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); in yellow_carp_is_dpm_running()
266 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0]; in yellow_carp_is_dpm_running()
A Daldebaran_ppt.c280 uint32_t *feature_mask, uint32_t num) in aldebaran_get_allowed_feature_mask() argument
286 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); in aldebaran_get_allowed_feature_mask()
928 uint32_t feature_mask, in aldebaran_upload_dpm_level() argument
937 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { in aldebaran_upload_dpm_level()
951 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { in aldebaran_upload_dpm_level()
965 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { in aldebaran_upload_dpm_level()
1458 uint32_t feature_mask[2]; in aldebaran_is_dpm_running() local
1461 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); in aldebaran_is_dpm_running()
1464 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | in aldebaran_is_dpm_running()
1465 ((uint64_t)feature_mask[1] << 32)); in aldebaran_is_dpm_running()
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A Dsmu_v13_0.c721 uint32_t feature_mask[2]; in smu_v13_0_set_allowed_mask() local
727 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64); in smu_v13_0_set_allowed_mask()
730 feature_mask[1], NULL); in smu_v13_0_set_allowed_mask()
735 feature_mask[0], NULL); in smu_v13_0_set_allowed_mask()
770 uint32_t feature_mask[2]; in smu_v13_0_system_features_control() local
782 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); in smu_v13_0_system_features_control()
786 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, in smu_v13_0_system_features_control()
788 bitmap_copy(feature->supported, (unsigned long *)&feature_mask, in smu_v13_0_system_features_control()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dnavi10_ppt.c280 uint32_t *feature_mask, uint32_t num) in navi10_get_allowed_feature_mask() argument
287 memset(feature_mask, 0, sizeof(uint32_t) * num); in navi10_get_allowed_feature_mask()
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); in navi10_get_allowed_feature_mask()
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in navi10_get_allowed_feature_mask()
335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); in navi10_get_allowed_feature_mask()
338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); in navi10_get_allowed_feature_mask()
341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); in navi10_get_allowed_feature_mask()
359 *(uint64_t *)feature_mask &= in navi10_get_allowed_feature_mask()
1667 uint32_t feature_mask[2]; in navi10_is_dpm_running() local
1670 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); in navi10_is_dpm_running()
[all …]
A Dcyan_skillfish_ppt.c379 uint32_t feature_mask[2]; in cyan_skillfish_is_dpm_running() local
386 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); in cyan_skillfish_is_dpm_running()
390 feature_enabled = (uint64_t)feature_mask[0] | in cyan_skillfish_is_dpm_running()
391 ((uint64_t)feature_mask[1] << 32); in cyan_skillfish_is_dpm_running()
A Darcturus_ppt.c328 uint32_t *feature_mask, uint32_t num) in arcturus_get_allowed_feature_mask() argument
334 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); in arcturus_get_allowed_feature_mask()
966 uint32_t feature_mask, in arcturus_upload_dpm_level() argument
975 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { in arcturus_upload_dpm_level()
989 (feature_mask & FEATURE_DPM_UCLK_MASK)) { in arcturus_upload_dpm_level()
1003 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { in arcturus_upload_dpm_level()
2052 uint32_t feature_mask[2]; in arcturus_is_dpm_running() local
2055 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); in arcturus_is_dpm_running()
2059 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0]; in arcturus_is_dpm_running()
2286 uint32_t feature_mask; member
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A Dsienna_cichlid_ppt.c265 uint32_t *feature_mask, uint32_t num) in sienna_cichlid_get_allowed_feature_mask() argument
272 memset(feature_mask, 0, sizeof(uint32_t) * num); in sienna_cichlid_get_allowed_feature_mask()
303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); in sienna_cichlid_get_allowed_feature_mask()
306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) in sienna_cichlid_get_allowed_feature_mask()
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); in sienna_cichlid_get_allowed_feature_mask()
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); in sienna_cichlid_get_allowed_feature_mask()
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in sienna_cichlid_get_allowed_feature_mask()
342 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); in sienna_cichlid_get_allowed_feature_mask()
1300 uint32_t feature_mask[2]; in sienna_cichlid_is_dpm_running() local
1303 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); in sienna_cichlid_is_dpm_running()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dvega10_smumgr.h46 bool enable, uint32_t feature_mask);
A Dvega12_smumgr.h52 bool enable, uint64_t feature_mask);
A Dvega20_smumgr.h51 bool enable, uint64_t feature_mask);
A Dvega12_smumgr.c126 bool enable, uint64_t feature_mask) in vega12_enable_smc_features() argument
130 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega12_enable_smc_features()
131 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega12_enable_smc_features()
A Dvega20_smumgr.c318 bool enable, uint64_t feature_mask) in vega20_enable_smc_features() argument
323 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega20_enable_smc_features()
324 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega20_enable_smc_features()
/linux/drivers/net/
A Dtap.c924 netdev_features_t feature_mask = 0; in set_offload() local
933 feature_mask = NETIF_F_HW_CSUM; in set_offload()
937 feature_mask |= NETIF_F_TSO_ECN; in set_offload()
939 feature_mask |= NETIF_F_TSO; in set_offload()
941 feature_mask |= NETIF_F_TSO6; in set_offload()
953 if (feature_mask & (NETIF_F_TSO | NETIF_F_TSO6)) in set_offload()
961 tap->tap_features = feature_mask; in set_offload()
/linux/arch/x86/mm/
A Dmem_encrypt_identity.c507 unsigned long feature_mask; in sme_enable() local
542 feature_mask = (sev_status & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT; in sme_enable()
545 if (feature_mask == AMD_SME_BIT) { in sme_enable()
/linux/include/linux/mfd/
A Dkempld.h91 u32 feature_mask; member

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