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Searched refs:flush_mask (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_ctl.c38 u32 flush_mask; member
473 u32 flush_mask) in fix_sw_flush() argument
496 *flush_mask = 0; in fix_for_single_flush()
537 u32 flush_mask, bool start) in mdp5_ctl_commit() argument
547 flush_mask |= MDP5_CTL_FLUSH_CTL; in mdp5_ctl_commit()
551 flush_mask |= fix_sw_flush(ctl, pipeline, flush_mask); in mdp5_ctl_commit()
555 curr_ctl_flush_mask = flush_mask; in mdp5_ctl_commit()
560 ctl->flush_mask |= flush_mask; in mdp5_ctl_commit()
563 flush_mask |= ctl->flush_mask; in mdp5_ctl_commit()
564 ctl->flush_mask = 0; in mdp5_ctl_commit()
[all …]
A Dmdp5_crtc.c98 DBG("%s: flush=%08x", crtc->name, flush_mask); in crtc_flush()
100 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); in crtc_flush()
113 uint32_t flush_mask = 0; in crtc_flush_all() local
122 flush_mask |= mdp5_plane_get_flush(plane); in crtc_flush_all()
126 flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm); in crtc_flush_all()
130 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm); in crtc_flush_all()
132 return crtc_flush(crtc, flush_mask); in crtc_flush_all()
949 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); in mdp5_crtc_cursor_set() local
1010 crtc_flush(crtc, flush_mask); in mdp5_crtc_cursor_set()
1027 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); in mdp5_crtc_cursor_move() local
[all …]
A Dmdp5_mixer.h20 uint32_t flush_mask; /* used to commit LM registers */ member
A Dmdp5_pipe.h23 uint32_t flush_mask; /* used to commit pipe registers */ member
A Dmdp5_ctl.h73 u32 flush_mask, bool start);
A Dmdp5_mixer.c158 mixer->flush_mask = mdp_ctl_flush_mask_lm(lm->id); in mdp5_mixer_init()
A Dmdp5_pipe.c164 hwpipe->flush_mask = mdp_ctl_flush_mask_pipe(pipe); in mdp5_pipe_init()
A Dmdp5_plane.c971 mask = pstate->hwpipe->flush_mask; in mdp5_plane_get_flush()
974 mask |= pstate->r_hwpipe->flush_mask; in mdp5_plane_get_flush()
/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_crtc.c351 u32 flush_mask; in _dpu_crtc_blend_setup_mixer() local
366 dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); in _dpu_crtc_blend_setup_mixer()
398 mixer[lm_idx].flush_mask |= flush_mask; in _dpu_crtc_blend_setup_mixer()
431 mixer[i].flush_mask = 0; in _dpu_crtc_blend_setup()
448 mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, in _dpu_crtc_blend_setup()
452 ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); in _dpu_crtc_blend_setup()
458 mixer[i].flush_mask); in _dpu_crtc_blend_setup()
702 mixer[i].flush_mask |= ctl->ops.get_bitmask_dspp(ctl, in _dpu_crtc_setup_cp_blocks()
706 ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); in _dpu_crtc_setup_cp_blocks()
711 mixer[i].flush_mask); in _dpu_crtc_setup_cp_blocks()
A Ddpu_crtc.h98 u32 flush_mask; member
/linux/drivers/infiniband/hw/irdma/
A Dhw.c2695 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) in irdma_flush_wqes() argument
2701 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) in irdma_flush_wqes()
2705 info.sq = flush_mask & IRDMA_FLUSH_SQ; in irdma_flush_wqes()
2706 info.rq = flush_mask & IRDMA_FLUSH_RQ; in irdma_flush_wqes()
2708 if (flush_mask & IRDMA_REFLUSH) { in irdma_flush_wqes()
2730 flush_mask & IRDMA_FLUSH_WAIT); in irdma_flush_wqes()
A Dmain.h469 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask);

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