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Searched refs:gate (Results 1 – 25 of 451) sorted by relevance

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/linux/drivers/clk/tegra/
A Dclk-periph-gate.c20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
41 if (!(read_enb(gate) & periph_clk_to_bit(gate))) in clk_periph_is_enabled()
45 if (read_rst(gate) & periph_clk_to_bit(gate)) in clk_periph_is_enabled()
55 write_enb_set(periph_clk_to_bit(gate), gate); in clk_periph_enable_locked()
78 write_enb_clr(periph_clk_to_bit(gate), gate); in clk_periph_disable_locked()
88 if (!gate->enable_refcnt[gate->clk_num]++) in clk_periph_enable()
103 WARN_ON(!gate->enable_refcnt[gate->clk_num]); in clk_periph_disable()
105 if (--gate->enable_refcnt[gate->clk_num] == 0) in clk_periph_disable()
123 if (!gate->enable_refcnt[gate->clk_num]) in clk_periph_disable_unused()
[all …]
/linux/drivers/clk/mmp/
A Dclk-gate.c34 if (gate->lock) in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
60 if (gate->lock) in mmp_clk_gate_disable()
68 if (gate->lock) in mmp_clk_gate_disable()
78 if (gate->lock) in mmp_clk_gate_is_enabled()
83 if (gate->lock) in mmp_clk_gate_is_enabled()
86 return (tmp & gate->mask) == gate->val_enable; in mmp_clk_gate_is_enabled()
105 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in mmp_clk_register_gate()
106 if (!gate) in mmp_clk_register_gate()
116 gate->reg = reg; in mmp_clk_register_gate()
[all …]
/linux/drivers/clk/imx/
A Dclk-gate2.c47 reg &= ~(gate->cgr_mask << gate->bit_idx); in clk_gate2_do_shared_clks()
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx; in clk_gate2_do_shared_clks()
60 if (gate->share_count && (*gate->share_count)++ > 0) in clk_gate2_enable()
108 ret = clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx, in clk_gate2_is_enabled()
109 gate->cgr_val, gate->cgr_mask); in clk_gate2_is_enabled()
123 if (!gate->share_count || *gate->share_count == 0) in clk_gate2_disable_unused()
148 if (!gate) in clk_hw_register_gate2()
152 gate->reg = reg; in clk_hw_register_gate2()
157 gate->lock = lock; in clk_hw_register_gate2()
167 hw = &gate->hw; in clk_hw_register_gate2()
[all …]
A Dclk-gate-exclusive.c25 struct clk_gate gate; member
33 struct clk_gate_exclusive, gate); in clk_gate_exclusive_enable()
34 u32 val = readl(gate->reg); in clk_gate_exclusive_enable()
62 struct clk_gate *gate; in imx_clk_hw_gate_exclusive() local
73 gate = &exgate->gate; in imx_clk_hw_gate_exclusive()
81 gate->reg = reg; in imx_clk_hw_gate_exclusive()
82 gate->bit_idx = shift; in imx_clk_hw_gate_exclusive()
83 gate->lock = &imx_ccm_lock; in imx_clk_hw_gate_exclusive()
84 gate->hw.init = &init; in imx_clk_hw_gate_exclusive()
87 hw = &gate->hw; in imx_clk_hw_gate_exclusive()
[all …]
A Dclk-composite-7ulp.c40 spin_lock_irqsave(gate->lock, flags); in pcc_gate_enable()
45 val = readl(gate->reg); in pcc_gate_enable()
47 writel(val, gate->reg); in pcc_gate_enable()
78 struct clk_gate *gate = NULL; in imx_ulp_clk_hw_composite() local
115 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in imx_ulp_clk_hw_composite()
116 if (!gate) { in imx_ulp_clk_hw_composite()
121 gate_hw = &gate->hw; in imx_ulp_clk_hw_composite()
122 gate->reg = reg; in imx_ulp_clk_hw_composite()
123 gate->bit_idx = PCG_CGC_SHIFT; in imx_ulp_clk_hw_composite()
125 gate->lock = &imx_ccm_lock; in imx_ulp_clk_hw_composite()
[all …]
/linux/drivers/clk/
A Dclk-gate.c31 return readl(gate->reg); in clk_gate_readl()
64 if (gate->lock) in clk_gate_endisable()
84 if (gate->lock) in clk_gate_endisable()
147 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in __clk_hw_register_gate()
148 if (!gate) in __clk_hw_register_gate()
163 gate->reg = reg; in __clk_hw_register_gate()
166 gate->lock = lock; in __clk_hw_register_gate()
169 hw = &gate->hw; in __clk_hw_register_gate()
175 kfree(gate); in __clk_hw_register_gate()
211 kfree(gate); in clk_unregister_gate()
[all …]
A Dclk-ast2600.c264 regmap_read(gate->map, get_reset_reg(gate), &reg); in aspeed_g6_clk_is_enabled()
270 regmap_read(gate->map, get_clock_reg(gate), &reg); in aspeed_g6_clk_is_enabled()
293 regmap_write(gate->map, get_reset_reg(gate), rst); in aspeed_g6_clk_enable()
301 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk); in aspeed_g6_clk_enable()
304 regmap_write(gate->map, get_clock_reg(gate), clk); in aspeed_g6_clk_enable()
311 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst); in aspeed_g6_clk_enable()
328 regmap_write(gate->map, get_clock_reg(gate), clk); in aspeed_g6_clk_disable()
331 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk); in aspeed_g6_clk_disable()
396 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in aspeed_g6_clk_hw_register_gate()
397 if (!gate) in aspeed_g6_clk_hw_register_gate()
[all …]
A Dclk-aspeed.c198 if (gate->reset_idx >= 0) { in aspeed_clk_is_enabled()
224 if (gate->reset_idx >= 0) { in aspeed_clk_enable()
236 if (gate->reset_idx >= 0) { in aspeed_clk_enable()
355 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in aspeed_clk_hw_register_gate()
356 if (!gate) in aspeed_clk_hw_register_gate()
365 gate->map = map; in aspeed_clk_hw_register_gate()
366 gate->clock_idx = clock_idx; in aspeed_clk_hw_register_gate()
369 gate->lock = lock; in aspeed_clk_hw_register_gate()
370 gate->hw.init = &init; in aspeed_clk_hw_register_gate()
372 hw = &gate->hw; in aspeed_clk_hw_register_gate()
[all …]
/linux/drivers/staging/sm750fb/
A Dddk750_power.c78 poke32(MODE1_GATE, gate); in sm750_set_current_gate()
80 poke32(MODE0_GATE, gate); in sm750_set_current_gate()
88 u32 gate; in sm750_enable_2d_engine() local
101 u32 gate; in sm750_enable_dma() local
106 gate |= CURRENT_GATE_DMA; in sm750_enable_dma()
108 gate &= ~CURRENT_GATE_DMA; in sm750_enable_dma()
118 u32 gate; in sm750_enable_gpio() local
123 gate |= CURRENT_GATE_GPIO; in sm750_enable_gpio()
135 u32 gate; in sm750_enable_i2c() local
140 gate |= CURRENT_GATE_I2C; in sm750_enable_i2c()
[all …]
/linux/arch/ia64/kernel/
A DMakefile.gate4 targets += gate.so gate.lds gate.o gate-dummy.o
6 obj-y += gate-syms.o
13 GATECFLAGS_gate.so = -shared -s -Wl,-soname=linux-gate.so.1 \
15 $(obj)/gate.so: $(obj)/gate.lds $(obj)/gate.o FORCE
16 $(call if_changed,gate)
19 $(obj)/gate-dummy.o: $(obj)/gate.lds $(obj)/gate.o FORCE
20 $(call if_changed,gate)
23 $(obj)/gate-syms.o: $(obj)/gate-dummy.o FORCE
29 $(obj)/gate-data.o: $(obj)/gate.so
/linux/Documentation/devicetree/bindings/clock/ti/
A Dgate.txt1 Binding for Texas Instruments gate clock.
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
22 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
23 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
26 "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
28 "ti,composite-gate-clock" - composite gate clock, to be part of composite
30 "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
36 ti,clkdm-gate-clock type
[all …]
/linux/drivers/clk/uniphier/
A Dclk-uniphier-gate.c27 return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit), in uniphier_clk_gate_endisable()
28 enable ? BIT(gate->bit) : 0); in uniphier_clk_gate_endisable()
47 if (regmap_read(gate->regmap, gate->reg, &val) < 0) in uniphier_clk_gate_is_enabled()
64 struct uniphier_clk_gate *gate; in uniphier_clk_register_gate() local
68 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); in uniphier_clk_register_gate()
69 if (!gate) in uniphier_clk_register_gate()
78 gate->regmap = regmap; in uniphier_clk_register_gate()
79 gate->reg = data->reg; in uniphier_clk_register_gate()
80 gate->bit = data->bit; in uniphier_clk_register_gate()
81 gate->hw.init = &init; in uniphier_clk_register_gate()
[all …]
/linux/drivers/clk/ingenic/
A Djz4770-cgu.c173 .gate = { CGU_REG_CLKGR1, 7 },
229 .gate = { CGU_REG_CLKGR0, 26 },
243 .gate = { CGU_REG_CLKGR1, 9 },
250 .gate = { CGU_REG_CLKGR0, 1 },
297 .gate = { CGU_REG_CLKGR0, 2 },
305 .gate = { CGU_REG_CLKGR0, 4 },
320 .gate = { CGU_REG_CLKGR1, 8 },
335 .gate = { CGU_REG_CLKGR0, 5 },
340 .gate = { CGU_REG_CLKGR0, 6 },
380 .gate = { CGU_REG_CLKGR0, 8 },
[all …]
A Djz4780-cgu.c394 .gate = { CGU_REG_CLKGR1, 2 },
436 .gate = { CGU_REG_CLKGR0, 3 },
494 .gate = { CGU_REG_CLKGR1, 3 },
503 .gate = { CGU_REG_CLKGR1, 4 },
512 .gate = { CGU_REG_CLKGR1, 9 },
521 .gate = { CGU_REG_CLKGR0, 1 },
541 .gate = { CGU_REG_CLKGR0, 0 },
547 .gate = { CGU_REG_CLKGR0, 2 },
553 .gate = { CGU_REG_CLKGR0, 4 },
559 .gate = { CGU_REG_CLKGR0, 5 },
[all …]
A Djz4760-cgu.c211 .gate = { CGU_REG_CLKGR0, 24 },
218 .gate = { CGU_REG_CLKGR1, 9 },
230 .gate = { CGU_REG_CLKGR0, 27 },
254 .gate = { CGU_REG_CLKGR1, 8 },
269 .gate = { CGU_REG_CLKGR0, 2 },
299 .gate = { CGU_REG_CLKGR0, 4 },
319 .gate = { CGU_REG_CLKGR0, 5 },
324 .gate = { CGU_REG_CLKGR0, 6 },
359 .gate = { CGU_REG_CLKGR0, 8 },
369 .gate = { CGU_REG_CLKGR0, 3 },
[all …]
A Dx1830-cgu.c279 .gate = { CGU_REG_CLKGR1, 4 },
288 .gate = { CGU_REG_CLKGR1, 9 },
302 .gate = { CGU_REG_CLKGR0, 4 },
309 .gate = { CGU_REG_CLKGR0, 5 },
350 .gate = { CGU_REG_CLKGR0, 0 },
356 .gate = { CGU_REG_CLKGR0, 1 },
362 .gate = { CGU_REG_CLKGR0, 3 },
368 .gate = { CGU_REG_CLKGR0, 6 },
374 .gate = { CGU_REG_CLKGR0, 7 },
380 .gate = { CGU_REG_CLKGR0, 8 },
[all …]
A Djz4725b-cgu.c131 .gate = { CGU_REG_CLKGR, 13 },
138 .gate = { CGU_REG_CLKGR, 9 },
146 .gate = { CGU_REG_CLKGR, 6 },
154 .gate = { CGU_REG_CLKGR, 4 },
175 .gate = { CGU_REG_CLKGR, 0 },
181 .gate = { CGU_REG_CLKGR, 12 },
187 .gate = { CGU_REG_CLKGR, 7 },
193 .gate = { CGU_REG_CLKGR, 3 },
199 .gate = { CGU_REG_CLKGR, 5 },
205 .gate = { CGU_REG_CLKGR, 6 },
[all …]
A Djz4740-cgu.c146 .gate = { CGU_REG_CLKGR, 10 },
160 .gate = { CGU_REG_CLKGR, 6 },
168 .gate = { CGU_REG_CLKGR, 4 },
175 .gate = { CGU_REG_CLKGR, 7 },
182 .gate = { CGU_REG_CLKGR, 14 },
198 .gate = { CGU_REG_CLKGR, 0 },
204 .gate = { CGU_REG_CLKGR, 15 },
222 .gate = { CGU_REG_CLKGR, 8 },
228 .gate = { CGU_REG_CLKGR, 3 },
234 .gate = { CGU_REG_CLKGR, 5 },
[all …]
A Dx1000-cgu.c256 .gate = { CGU_REG_CLKGR, 30 },
288 .gate = { CGU_REG_CLKGR, 28 },
325 .gate = { CGU_REG_CLKGR, 4 },
332 .gate = { CGU_REG_CLKGR, 5 },
341 .gate = { CGU_REG_CLKGR, 3 },
381 .gate = { CGU_REG_CLKGR, 0 },
387 .gate = { CGU_REG_CLKGR, 1 },
393 .gate = { CGU_REG_CLKGR, 2 },
399 .gate = { CGU_REG_CLKGR, 7 },
405 .gate = { CGU_REG_CLKGR, 8 },
[all …]
/linux/drivers/clk/bcm/
A Dclk-kona.c364 if (!gate_exists(gate)) in __is_clk_gate_enabled()
381 if (!gate_exists(gate)) in is_clk_gate_enabled()
425 if (gate_is_sw_managed(gate) && (enabled = gate_is_enabled(gate)) && in __gate_commit()
438 return __ccu_wait_bit(ccu, gate->offset, gate->status_bit, enabled); in __gate_commit()
449 if (!gate_exists(gate)) in gate_init()
465 if (!gate_exists(gate) || !gate_is_sw_managed(gate)) in __clk_gate()
477 gate_flip_enabled(gate); in __clk_gate()
496 if (!gate_exists(gate) || !gate_is_sw_managed(gate)) in clk_gate()
977 struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate; in kona_peri_clk_enable() local
985 struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate; in kona_peri_clk_disable() local
[all …]
A Dclk-bcm281xx.c24 .gate = HW_SW_GATE(0x214, 16, 0, 1),
42 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
51 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
84 .gate = HW_SW_GATE(0x04a4, 18, 2, 3),
103 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
115 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
127 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
139 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
151 .gate = HW_SW_GATE(0x0354, 18, 2, 3),
162 .gate = HW_SW_GATE(0x0370, 18, 2, 3),
[all …]
A Dclk-bcm21664.c24 .gate = HW_SW_GATE(0x214, 16, 0, 1),
41 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
66 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
78 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
90 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
102 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
115 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
120 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
125 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
130 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
[all …]
/linux/drivers/clk/zynqmp/
A Dclk-gate-zynqmp.c38 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_enable()
58 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_disable()
78 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_is_enabled()
112 struct zynqmp_clk_gate *gate; in zynqmp_clk_register_gate() local
118 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in zynqmp_clk_register_gate()
119 if (!gate) in zynqmp_clk_register_gate()
131 gate->flags = nodes->type_flag; in zynqmp_clk_register_gate()
132 gate->hw.init = &init; in zynqmp_clk_register_gate()
133 gate->clk_id = clk_id; in zynqmp_clk_register_gate()
135 hw = &gate->hw; in zynqmp_clk_register_gate()
[all …]
/linux/drivers/clk/mediatek/
A Dclk-mtk.c136 clk = mtk_clk_register_gate(gate->name, gate->parent_name, in mtk_clk_register_gates_with_dev()
138 gate->regs->set_ofs, in mtk_clk_register_gates_with_dev()
139 gate->regs->clr_ofs, in mtk_clk_register_gates_with_dev()
140 gate->regs->sta_ofs, in mtk_clk_register_gates_with_dev()
141 gate->shift, gate->ops, gate->flags, dev); in mtk_clk_register_gates_with_dev()
169 struct clk_gate *gate = NULL; in mtk_clk_register_composite() local
200 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in mtk_clk_register_composite()
201 if (!gate) { in mtk_clk_register_composite()
209 gate->lock = lock; in mtk_clk_register_composite()
211 gate_hw = &gate->hw; in mtk_clk_register_composite()
[all …]
/linux/arch/x86/include/asm/
A Ddesc.h84 gate->bits.p = 1; in pack_gate()
85 gate->bits.dpl = dpl; in pack_gate()
86 gate->bits.zero = 0; in pack_gate()
87 gate->bits.type = type; in pack_gate()
91 gate->bits.ist = ist; in pack_gate()
92 gate->reserved = 0; in pack_gate()
95 gate->segment = seg; in pack_gate()
96 gate->bits.ist = 0; in pack_gate()
139 memcpy(&idt[entry], gate, sizeof(*gate)); in native_write_idt_entry()
426 gate->bits = d->bits; in idt_init_desc()
[all …]

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