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Searched refs:gpc (Results 1 – 25 of 69) sorted by relevance

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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
A Dctxgp100.c56 int gpc, ppc, b, n = 0; in gp100_grctx_generate_attrib() local
58 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp100_grctx_generate_attrib()
59 size += grctx->attrib_nr_max * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gp100_grctx_generate_attrib()
72 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp100_grctx_generate_attrib()
73 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gp100_grctx_generate_attrib()
74 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
77 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp100_grctx_generate_attrib()
78 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp100_grctx_generate_attrib()
86 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
104 const u8 gpc = gr->sm[sm].gpc; in gp100_grctx_generate_smid_config() local
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A Dgv100.c28 gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) in gv100_gr_trap_sm() argument
42 gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : ""); in gv100_gr_trap_sm()
45 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr); in gv100_gr_trap_sm()
49 gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) in gv100_gr_trap_mp() argument
51 gv100_gr_trap_sm(gr, gpc, tpc, 0); in gv100_gr_trap_mp()
52 gv100_gr_trap_sm(gr, gpc, tpc, 1); in gv100_gr_trap_mp()
68 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x728 + sm), 0x0085eb64); in gv100_gr_init_shader_exceptions()
69 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x610), 0x00000001); in gv100_gr_init_shader_exceptions()
70 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x72c + sm), 0x00000004); in gv100_gr_init_shader_exceptions()
75 gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) in gv100_gr_init_504430() argument
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A Dctxgp102.c52 int gpc, ppc, b, n = 0; in gp102_grctx_generate_attrib() local
54 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp102_grctx_generate_attrib()
55 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gp102_grctx_generate_attrib()
68 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_grctx_generate_attrib()
69 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gp102_grctx_generate_attrib()
70 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
74 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp102_grctx_generate_attrib()
75 const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); in gp102_grctx_generate_attrib()
76 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp102_grctx_generate_attrib()
85 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
A Dctxgm200.c55 const u8 gpc = gr->sm[sm].gpc; in gm200_grctx_generate_smid_config() local
57 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); in gm200_grctx_generate_smid_config()
58 gpcs[gpc] |= sm << (tpc * 8); in gm200_grctx_generate_smid_config()
87 int gpc, ppc, i; in gm200_grctx_generate_dist_skip_table() local
89 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gm200_grctx_generate_dist_skip_table()
90 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { in gm200_grctx_generate_dist_skip_table()
91 u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
92 u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
95 ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
96 ((u8 *)data)[gpc] |= ppc_tpcm; in gm200_grctx_generate_dist_skip_table()
A Dctxgv100.c73 int gpc, ppc, b, n = 0; in gv100_grctx_generate_attrib() local
75 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gv100_grctx_generate_attrib()
88 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gv100_grctx_generate_attrib()
89 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gv100_grctx_generate_attrib()
90 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
94 const u32 o = PPC_UNIT(gpc, ppc, 0); in gv100_grctx_generate_attrib()
95 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gv100_grctx_generate_attrib()
103 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
160 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); in gv100_grctx_generate_sm_id()
161 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm); in gv100_grctx_generate_sm_id()
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A Dctxgf100.c1072 int gpc, tpc; in gf100_grctx_generate_attrib() local
1079 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_attrib()
1275 int i, gpc; in gf100_grctx_generate_alpha_beta_tables() local
1287 for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
1288 if (abits[gpc] < gr->tpc_nr[gpc]) { in gf100_grctx_generate_alpha_beta_tables()
1295 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
1296 u32 bbits = gr->tpc_nr[gpc] - abits[gpc]; in gf100_grctx_generate_alpha_beta_tables()
1297 amask |= ((1 << abits[gpc]) - 1) << (gpc * 8); in gf100_grctx_generate_alpha_beta_tables()
1298 bmask |= ((1 << bbits) - 1) << abits[gpc] << (gpc * 8); in gf100_grctx_generate_alpha_beta_tables()
1310 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); in gf100_grctx_generate_tpc_nr()
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A Dgf100.c1355 int rop, gpc; in gf100_gr_trap_intr() local
1443 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { in gf100_gr_trap_intr()
1498 u32 gpc; in gf100_gr_ctxctl_debug() local
1501 for (gpc = 0; gpc < gpcnr; gpc++) in gf100_gr_ctxctl_debug()
1853 int tpc, gpc; in gf100_gr_oneinit_sm_id() local
1855 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_oneinit_sm_id()
1857 gr->sm[gr->sm_nr].gpc = gpc; in gf100_gr_oneinit_sm_id()
2174 int gpc, tpc; in gf100_gr_init_419cc0() local
2178 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_init_419cc0()
2237 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_init_zcull()
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A Dctxgm107.c921 int gpc, ppc, n = 0; in gm107_grctx_generate_attrib() local
929 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gm107_grctx_generate_attrib()
930 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gm107_grctx_generate_attrib()
931 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
932 const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
934 const u32 o = PPC_UNIT(gpc, ppc, 0); in gm107_grctx_generate_attrib()
935 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gm107_grctx_generate_attrib()
942 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
958 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), sm); in gm107_grctx_generate_sm_id()
959 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm); in gm107_grctx_generate_sm_id()
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A Dctxgf117.c257 int gpc, ppc; in gf117_grctx_generate_attrib() local
264 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_grctx_generate_attrib()
265 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { in gf117_grctx_generate_attrib()
266 const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
267 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
269 const u32 o = PPC_UNIT(gpc, ppc, 0); in gf117_grctx_generate_attrib()
270 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gf117_grctx_generate_attrib()
274 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
276 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
A Dgf117.c129 u8 bank[GPC_MAX] = {}, gpc, i, j; in gf117_gr_init_zcull() local
140 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_gr_init_zcull()
141 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in gf117_gr_init_zcull()
142 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in gf117_gr_init_zcull()
143 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in gf117_gr_init_zcull()
145 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in gf117_gr_init_zcull()
A Dtu102.c43 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + in tu102_gr_init_fs()
57 u8 bank[GPC_MAX] = {}, gpc, i, j; in tu102_gr_init_zcull() local
68 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in tu102_gr_init_zcull()
69 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in tu102_gr_init_zcull()
70 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in tu102_gr_init_zcull()
71 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in tu102_gr_init_zcull()
73 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in tu102_gr_init_zcull()
A Dctxgk104.c933 int i, j, gpc, ppc; in gk104_grctx_generate_alpha_beta_tables() local
941 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gk104_grctx_generate_alpha_beta_tables()
943 u32 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
954 pmask = gr->ppc_tpc_mask[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
957 amask |= (u64)pmask << (gpc * 8); in gk104_grctx_generate_alpha_beta_tables()
959 pmask ^= gr->ppc_tpc_mask[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
960 bmask |= (u64)pmask << (gpc * 8); in gk104_grctx_generate_alpha_beta_tables()
A Dgk104.c418 int gpc, ppc; in gk104_gr_init_ppc_exceptions() local
420 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gk104_gr_init_ppc_exceptions()
421 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { in gk104_gr_init_ppc_exceptions()
422 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gk104_gr_init_ppc_exceptions()
424 nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); in gk104_gr_init_ppc_exceptions()
A Dgp102.c89 u32 mask = 0, data, gpc; in gp102_gr_init_swdx_pes_mask() local
91 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_gr_init_swdx_pes_mask()
92 data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f; in gp102_gr_init_swdx_pes_mask()
93 mask |= data << (gpc * 4); in gp102_gr_init_swdx_pes_mask()
A Dctxgf108.c749 int gpc, tpc; in gf108_grctx_generate_attrib() local
756 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf108_grctx_generate_attrib()
757 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf108_grctx_generate_attrib()
761 const u32 o = TPC_UNIT(gpc, tpc, 0x500); in gf108_grctx_generate_attrib()
A Dctxtu102.c34 tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in tu102_grctx_generate_sm_id() argument
37 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); in tu102_grctx_generate_sm_id()
38 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); in tu102_grctx_generate_sm_id()
A Dgm107.c294 gm107_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) in gm107_gr_init_shader_exceptions() argument
297 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); in gm107_gr_init_shader_exceptions()
298 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); in gm107_gr_init_shader_exceptions()
302 gm107_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) in gm107_gr_init_504430() argument
305 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); in gm107_gr_init_504430()
/linux/Documentation/devicetree/bindings/power/
A Dfsl,imx-gpcv2.yaml27 - fsl,imx7d-gpc
28 - fsl,imx8mn-gpc
29 - fsl,imx8mq-gpc
30 - fsl,imx8mm-gpc
57 include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
58 include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
59 include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc
98 gpc@303a0000 {
99 compatible = "fsl,imx7d-gpc";
A Dfsl,imx-gpc.yaml4 $id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml#
27 - fsl,imx6q-gpc
28 - fsl,imx6qp-gpc
29 - fsl,imx6sl-gpc
30 - fsl,imx6sx-gpc
96 gpc@20dc000 {
97 compatible = "fsl,imx6q-gpc";
/linux/arch/mips/boot/dts/ingenic/
A Dqi_lb60.dts114 col-gpios = <&gpc 10 0>, <&gpc 11 0>, <&gpc 12 0>, <&gpc 13 0>,
115 <&gpc 14 0>, <&gpc 15 0>, <&gpc 16 0>, <&gpc 17 0>;
186 sck-gpios = <&gpc 23 GPIO_ACTIVE_HIGH>;
187 mosi-gpios = <&gpc 22 GPIO_ACTIVE_HIGH>;
188 cs-gpios = <&gpc 21 GPIO_ACTIVE_LOW>;
196 status-gpios = <&gpc 27 GPIO_ACTIVE_LOW>;
268 rb-gpios = <&gpc 30 GPIO_ACTIVE_HIGH>;
A Dcu1830-neo.dts29 gpios = <&gpc 17 GPIO_ACTIVE_HIGH>;
40 mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
41 miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
42 sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
43 cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
73 reset-gpios = <&gpc 13 GPIO_ACTIVE_LOW>;
153 interrupt-parent = <&gpc>;
A Drs90.dts61 gpios = <&gpc 10 GPIO_ACTIVE_LOW>;
67 gpios = <&gpc 11 GPIO_ACTIVE_LOW>;
85 gpios = <&gpc 31 GPIO_ACTIVE_LOW>;
91 gpios = <&gpc 30 GPIO_ACTIVE_LOW>;
97 gpios = <&gpc 12 GPIO_ACTIVE_LOW>;
130 enable-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
238 cd-gpios = <&gpc 20 GPIO_ACTIVE_LOW>;
268 rb-gpios = <&gpc 27 GPIO_ACTIVE_HIGH>;
A Dcu1000-neo.dts56 interrupt-parent = <&gpc>;
73 reset-gpios = <&gpc 17 GPIO_ACTIVE_LOW>;
149 interrupt-parent = <&gpc>;
166 snps,reset-gpio = <&gpc 23 GPIO_ACTIVE_LOW>; /* PC23 */
/linux/arch/arm/mach-imx/
A Dcpu-imx5.c129 u32 gpc; in imx5_pmu_init() local
151 gpc = readl_relaxed(tigerp_base + ARM_GPC); in imx5_pmu_init()
152 gpc |= DBGEN; in imx5_pmu_init()
153 writel_relaxed(gpc, tigerp_base + ARM_GPC); in imx5_pmu_init()
/linux/arch/arm/boot/dts/
A Ds3c64xx-pinctrl.dtsi33 gpc: gpc { label
214 samsung,pins = "gpc-0", "gpc-1", "gpc-2";
220 samsung,pins = "gpc-3";
226 samsung,pins = "gpc-4", "gpc-5", "gpc-6";
232 samsung,pins = "gpc-7";
305 samsung,pins = "gpc-4";
311 samsung,pins = "gpc-5";
354 samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6",

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