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Searched refs:gpu_write (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/msm/adreno/
A Da3xx_gpu.c211 gpu_write(gpu, REG_A3XX_RBBM_SP_HYST_CNT, 0x10); in a3xx_hw_init()
250 gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR, in a3xx_hw_init()
255 gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01); in a3xx_hw_init()
273 gpu_write(gpu, REG_AXXX_CP_RB_CNTL, in a3xx_hw_init()
314 gpu_write(gpu, REG_AXXX_CP_DEBUG, in a3xx_hw_init()
317 gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0); in a3xx_hw_init()
326 gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0); in a3xx_hw_init()
333 gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, in a3xx_hw_init()
347 gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0); in a3xx_hw_init()
367 gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1); in a3xx_recover()
[all …]
A Da4xx_gpu.c109 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_RB(i), in a4xx_enable_hwcg()
112 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_RB(i), in a4xx_enable_hwcg()
150 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0); in a4xx_enable_hwcg()
153 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2, 0); in a4xx_enable_hwcg()
240 gpu_write(gpu, REG_A4XX_RB_GMEM_BASE_ADDR, in a4xx_hw_init()
258 gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) | in a4xx_hw_init()
322 gpu_write(gpu, REG_A4XX_CP_RB_CNTL, in a4xx_hw_init()
332 gpu_write(gpu, REG_A4XX_CP_ME_RAM_WADDR, 0); in a4xx_hw_init()
341 gpu_write(gpu, REG_A4XX_CP_PFP_UCODE_ADDR, 0); in a4xx_hw_init()
346 gpu_write(gpu, REG_A4XX_CP_ME_CNTL, 0); in a4xx_hw_init()
[all …]
A Da5xx_power.c130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
151 gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x201FF1); in a530_lm_setup()
153 gpu_write(gpu, AGC_MSG_STATE, 1); in a530_lm_setup()
157 gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448); in a530_lm_setup()
158 gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1); in a530_lm_setup()
193 gpu_write(gpu, AGC_MSG_STATE, 0x80000001); in a540_lm_setup()
196 gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448); in a540_lm_setup()
197 gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1); in a540_lm_setup()
204 gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, in a540_lm_setup()
286 gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0); in a5xx_lm_enable()
[all …]
A Da2xx_gpu.c154 gpu_write(gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_hw_init()
158 gpu_write(gpu, REG_A2XX_MH_ARBITER_CONFIG, in a2xx_hw_init()
184 gpu_write(gpu, REG_A2XX_RBBM_INT_CNTL, in a2xx_hw_init()
186 gpu_write(gpu, REG_AXXX_CP_INT_CNTL, in a2xx_hw_init()
194 gpu_write(gpu, REG_A2XX_SQ_INT_CNTL, 0); in a2xx_hw_init()
195 gpu_write(gpu, REG_A2XX_MH_INTERRUPT_MASK, in a2xx_hw_init()
203 gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i); in a2xx_hw_init()
209 gpu_write(gpu, REG_AXXX_CP_RB_CNTL, in a2xx_hw_init()
225 gpu_write(gpu, REG_AXXX_CP_DEBUG, in a2xx_hw_init()
227 gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0); in a2xx_hw_init()
[all …]
A Da5xx_gpu.c63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
456 gpu_write(gpu, regs[i].offset, in a5xx_set_hwcg()
755 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
759 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
762 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
831 gpu_write(gpu, REG_A5XX_CP_PROTECT(6), in a5xx_hw_init()
834 gpu_write(gpu, REG_A5XX_CP_PROTECT(7), in a5xx_hw_init()
857 gpu_write(gpu, REG_A5XX_CP_PROTECT(17), in a5xx_hw_init()
916 gpu_write(gpu, REG_A5XX_CP_RB_CNTL, in a5xx_hw_init()
946 gpu_write(gpu, REG_A5XX_CP_PFP_ME_CNTL, 0); in a5xx_hw_init()
[all …]
A Da6xx_gpu.c88 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in a6xx_flush()
719 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, in a6xx_set_ubwc_config()
722 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, in a6xx_set_ubwc_config()
959 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); in hw_init()
987 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); in hw_init()
1001 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); in hw_init()
1020 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); in hw_init()
1030 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, in hw_init()
1056 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, in hw_init()
1087 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); in hw_init()
[all …]
A Da6xx_gpu_state.c145 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
150 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
209 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
212 gpu_write(gpu, ctrl1, i); in vbif_debugbus_read()
246 gpu_write(gpu, REG_A6XX_VBIF_CLKON, in a6xx_get_vbif_debugbus_block()
250 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
279 gpu_write(gpu, REG_A6XX_VBIF_CLKON, clk); in a6xx_get_vbif_debugbus_block()
327 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLT, in a6xx_get_debugbus()
330 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLM, in a6xx_get_debugbus()
877 gpu_write(gpu, indexed->addr, 0); in a6xx_get_indexed_regs()
[all …]
A Da5xx_debugfs.c21 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
34 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
45 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
58 gpu_write(gpu, REG_A5XX_CP_ROQ_DBG_ADDR, 0); in roq_print()
A Da5xx_preempt.c52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
155 gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); in a5xx_preempt_trigger()
A Da6xx_gmu.c1021 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); in a6xx_bus_clear_pending_transactions()
1024 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); in a6xx_bus_clear_pending_transactions()
1030 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); in a6xx_bus_clear_pending_transactions()
1035 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); in a6xx_bus_clear_pending_transactions()
1040 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); in a6xx_bus_clear_pending_transactions()
A Dadreno_gpu.c483 gpu_write(gpu, reg, wptr); in adreno_flush()
/linux/drivers/gpu/drm/panfrost/
A Dpanfrost_perfcnt.c56 gpu_write(pfdev, GPU_INT_CLEAR, in panfrost_perfcnt_dump_locked()
118 gpu_write(pfdev, GPU_INT_CLEAR, in panfrost_perfcnt_enable_locked()
152 gpu_write(pfdev, GPU_PRFCNT_TILER_EN, 0); in panfrost_perfcnt_enable_locked()
156 gpu_write(pfdev, GPU_PERFCNT_CFG, cfg); in panfrost_perfcnt_enable_locked()
189 gpu_write(pfdev, GPU_PRFCNT_JM_EN, 0x0); in panfrost_perfcnt_disable_locked()
192 gpu_write(pfdev, GPU_PRFCNT_TILER_EN, 0); in panfrost_perfcnt_disable_locked()
193 gpu_write(pfdev, GPU_PERFCNT_CFG, in panfrost_perfcnt_disable_locked()
325 gpu_write(pfdev, GPU_PERFCNT_CFG, in panfrost_perfcnt_init()
327 gpu_write(pfdev, GPU_PRFCNT_JM_EN, 0); in panfrost_perfcnt_init()
342 gpu_write(pfdev, GPU_PERFCNT_CFG, in panfrost_perfcnt_fini()
[all …]
A Dpanfrost_gpu.c42 gpu_write(pfdev, GPU_INT_MASK, 0); in panfrost_gpu_irq_handler()
51 gpu_write(pfdev, GPU_INT_CLEAR, state); in panfrost_gpu_irq_handler()
61 gpu_write(pfdev, GPU_INT_MASK, 0); in panfrost_gpu_soft_reset()
63 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); in panfrost_gpu_soft_reset()
115 gpu_write(pfdev, GPU_SHADER_CONFIG, quirks); in panfrost_gpu_init_quirks()
124 gpu_write(pfdev, GPU_TILER_CONFIG, quirks); in panfrost_gpu_init_quirks()
137 gpu_write(pfdev, GPU_L2_MMU_CONFIG, quirks); in panfrost_gpu_init_quirks()
149 gpu_write(pfdev, GPU_JM_CONFIG, quirks); in panfrost_gpu_init_quirks()
348 gpu_write(pfdev, TILER_PWROFF_LO, 0); in panfrost_gpu_power_off()
349 gpu_write(pfdev, SHADER_PWROFF_LO, 0); in panfrost_gpu_power_off()
[all …]
A Dpanfrost_regs.h321 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg) macro
/linux/drivers/gpu/drm/etnaviv/
A Detnaviv_iommu.c100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
110 gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
111 gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
112 gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
113 gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
A Detnaviv_iommu_v2.c186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
203 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
207 gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
209 gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
211 gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
213 gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG, in etnaviv_iommuv2_restore_sec()
228 gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
A Detnaviv_gpu.c468 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
470 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
511 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
594 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); in etnaviv_gpu_enable_mlcg()
631 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); in etnaviv_gpu_enable_mlcg()
637 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
722 gpu_write(gpu, VIVS_HI_AXI_CONFIG, in etnaviv_gpu_hw_init()
745 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); in etnaviv_gpu_hw_init()
1299 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); in sync_point_perfmon_sample_pre()
1304 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_pre()
[all …]
A Detnaviv_perfmon.c44 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read()
54 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_select()
A Detnaviv_gpu.h151 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/linux/drivers/gpu/drm/msm/
A Dmsm_gpummu.c50 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in msm_gpummu_map()
65 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in msm_gpummu_unmap()
A Dmsm_gpu.h424 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/linux/drivers/gpu/drm/i915/gem/selftests/
A Dhuge_pages.c979 static int gpu_write(struct intel_context *ce, in gpu_write() function
1103 err = gpu_write(ce, vma, dword, val); in __igt_write_huge()
1571 err = gpu_write(ce, vma, n++, 0xdeadbeaf); in igt_shrink_thp()

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