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Searched refs:grph (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_hubbub.c343 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub3_get_dcc_compression_cap()
344 output->grph.rgb.max_compressed_blk_size = 256; in hubbub3_get_dcc_compression_cap()
345 output->grph.rgb.independent_64b_blks = false; in hubbub3_get_dcc_compression_cap()
350 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub3_get_dcc_compression_cap()
351 output->grph.rgb.max_compressed_blk_size = 128; in hubbub3_get_dcc_compression_cap()
352 output->grph.rgb.independent_64b_blks = false; in hubbub3_get_dcc_compression_cap()
358 output->grph.rgb.max_compressed_blk_size = 64; in hubbub3_get_dcc_compression_cap()
359 output->grph.rgb.independent_64b_blks = true; in hubbub3_get_dcc_compression_cap()
360 output->grph.rgb.dcc_controls.dcc_256_64_64 = 1; in hubbub3_get_dcc_compression_cap()
364 output->grph.rgb.max_compressed_blk_size = 128; in hubbub3_get_dcc_compression_cap()
[all …]
A Ddcn30_hubp.c112 if (address->grph.addr.quad_part == 0) in hubp3_program_surface_flip_and_addr()
119 if (address->grph.meta_addr.quad_part != 0) { in hubp3_program_surface_flip_and_addr()
122 address->grph.meta_addr.high_part); in hubp3_program_surface_flip_and_addr()
126 address->grph.meta_addr.low_part); in hubp3_program_surface_flip_and_addr()
131 address->grph.addr.high_part); in hubp3_program_surface_flip_and_addr()
135 address->grph.addr.low_part); in hubp3_program_surface_flip_and_addr()
A Ddcn30_hwseq.c774 plane->address.grph.cursor_cache_addr.quad_part; in dcn30_apply_idle_power_optimizations()
881 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047; in dcn30_apply_idle_power_optimizations()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_hubbub.c285 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
286 output->grph.rgb.max_compressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
287 output->grph.rgb.independent_64b_blks = false; in hubbub2_get_dcc_compression_cap()
290 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub2_get_dcc_compression_cap()
291 output->grph.rgb.max_compressed_blk_size = 128; in hubbub2_get_dcc_compression_cap()
292 output->grph.rgb.independent_64b_blks = false; in hubbub2_get_dcc_compression_cap()
295 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
296 output->grph.rgb.max_compressed_blk_size = 64; in hubbub2_get_dcc_compression_cap()
297 output->grph.rgb.independent_64b_blks = true; in hubbub2_get_dcc_compression_cap()
A Ddcn20_hubp.c737 if (address->grph.addr.quad_part == 0) in hubp2_program_surface_flip_and_addr()
744 if (address->grph.meta_addr.quad_part != 0) { in hubp2_program_surface_flip_and_addr()
747 address->grph.meta_addr.high_part); in hubp2_program_surface_flip_and_addr()
751 address->grph.meta_addr.low_part); in hubp2_program_surface_flip_and_addr()
756 address->grph.addr.high_part); in hubp2_program_surface_flip_and_addr()
760 address->grph.addr.low_part); in hubp2_program_surface_flip_and_addr()
917 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); in hubp2_is_flip_pending()
920 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); in hubp2_is_flip_pending()
925 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp2_is_flip_pending()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_hubbub.c844 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub31_get_dcc_compression_cap()
845 output->grph.rgb.max_compressed_blk_size = 256; in hubbub31_get_dcc_compression_cap()
846 output->grph.rgb.independent_64b_blks = false; in hubbub31_get_dcc_compression_cap()
851 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub31_get_dcc_compression_cap()
852 output->grph.rgb.max_compressed_blk_size = 128; in hubbub31_get_dcc_compression_cap()
853 output->grph.rgb.independent_64b_blks = false; in hubbub31_get_dcc_compression_cap()
859 output->grph.rgb.max_compressed_blk_size = 64; in hubbub31_get_dcc_compression_cap()
860 output->grph.rgb.independent_64b_blks = true; in hubbub31_get_dcc_compression_cap()
861 output->grph.rgb.dcc_controls.dcc_256_64_64 = 1; in hubbub31_get_dcc_compression_cap()
865 output->grph.rgb.max_compressed_blk_size = 128; in hubbub31_get_dcc_compression_cap()
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/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hubbub.c909 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
910 output->grph.rgb.max_compressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
911 output->grph.rgb.independent_64b_blks = false; in hubbub1_get_dcc_compression_cap()
914 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub1_get_dcc_compression_cap()
915 output->grph.rgb.max_compressed_blk_size = 128; in hubbub1_get_dcc_compression_cap()
916 output->grph.rgb.independent_64b_blks = false; in hubbub1_get_dcc_compression_cap()
919 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
920 output->grph.rgb.max_compressed_blk_size = 64; in hubbub1_get_dcc_compression_cap()
921 output->grph.rgb.independent_64b_blks = true; in hubbub1_get_dcc_compression_cap()
A Ddcn10_hubp.c388 if (address->grph.addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
395 if (address->grph.meta_addr.quad_part != 0) { in hubp1_program_surface_flip_and_addr()
398 address->grph.meta_addr.high_part); in hubp1_program_surface_flip_and_addr()
402 address->grph.meta_addr.low_part); in hubp1_program_surface_flip_and_addr()
407 address->grph.addr.high_part); in hubp1_program_surface_flip_and_addr()
411 address->grph.addr.low_part); in hubp1_program_surface_flip_and_addr()
744 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); in hubp1_is_flip_pending()
747 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); in hubp1_is_flip_pending()
752 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp1_is_flip_pending()
/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc_debug.c83 plane_state->address.grph.addr.quad_part, in pre_surface_trace()
84 plane_state->address.grph.meta_addr.quad_part, in pre_surface_trace()
195 update->flip_addr->address.grph.addr.quad_part, in update_surface_trace()
196 update->flip_addr->address.grph.meta_addr.quad_part, in update_surface_trace()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_hubp.c711 if (address->grph.addr.quad_part == 0) { in hubp21_program_surface_flip_and_addr()
716 if (address->grph.meta_addr.quad_part != 0) { in hubp21_program_surface_flip_and_addr()
718 address->grph.meta_addr.low_part; in hubp21_program_surface_flip_and_addr()
720 address->grph.meta_addr.high_part; in hubp21_program_surface_flip_and_addr()
724 address->grph.addr.low_part; in hubp21_program_surface_flip_and_addr()
726 address->grph.addr.high_part; in hubp21_program_surface_flip_and_addr()
/linux/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_hw_sequencer.c351 pipe_ctx->plane_state->address.grph.addr.high_part, in dce60_program_front_end_for_pipe()
352 pipe_ctx->plane_state->address.grph.addr.low_part, in dce60_program_front_end_for_pipe()
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_mem_input.c853 if (address->grph.addr.quad_part == 0) in dce_mi_program_surface_flip_and_addr()
855 program_pri_addr(dce_mi, address->grph.addr); in dce_mi_program_surface_flip_and_addr()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_hwseq.c110 gpu_addr_to_uma(hwseq, &addr->grph.addr); in plane_address_in_gpu_space_to_uma()
111 gpu_addr_to_uma(hwseq, &addr->grph.meta_addr); in plane_address_in_gpu_space_to_uma()
/linux/drivers/gpu/drm/amd/display/dc/
A Ddc_hw_types.h77 } grph; member
A Ddc.h228 } grph; member
/linux/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_mem_input_v.c138 addr->grph.addr); in program_addr()
A Ddce110_hw_sequencer.c2824 pipe_ctx->plane_state->address.grph.addr.high_part,
2825 pipe_ctx->plane_state->address.grph.addr.low_part,
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm.c4793 output.grph.rgb.independent_64b_blks != 0) in validate_dcc()
5249 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); in fill_gfx9_plane_attributes_from_modifiers()
5250 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); in fill_gfx9_plane_attributes_from_modifiers()
5294 address->grph.addr.low_part = lower_32_bits(addr); in fill_plane_buffer_attributes()
5295 address->grph.addr.high_part = upper_32_bits(addr); in fill_plane_buffer_attributes()
9130 bundle->flip_addrs[planes_count].address.grph.addr.high_part, in amdgpu_dm_commit_planes()
9131 bundle->flip_addrs[planes_count].address.grph.addr.low_part); in amdgpu_dm_commit_planes()

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