Searched refs:harvest_config (Results 1 – 16 of 16) sorted by relevance
65 adev->jpeg.harvest_config |= 1 << i; in jpeg_v2_5_early_init()91 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_sw_init()110 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_sw_init()163 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_hw_init()195 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_hw_fini()303 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_start()357 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_stop()468 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_is_idle()485 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_wait_for_idle()506 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_set_clockgating_state()[all …]
83 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_get_rptr()84 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_get_rptr()86 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) in vce_v3_0_ring_get_rptr()115 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_get_wptr()116 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_get_wptr()146 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_set_wptr()147 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_set_wptr()272 if (adev->vce.harvest_config & (1 << idx)) in vce_v3_0_start()337 if (adev->vce.harvest_config & (1 << idx)) in vce_v3_0_stop()405 if ((adev->vce.harvest_config & in vce_v3_0_early_init()[all …]
81 adev->vcn.harvest_config = 0; in vcn_v2_5_early_init()90 adev->vcn.harvest_config |= 1 << i; in vcn_v2_5_early_init()121 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_sw_init()151 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_sw_init()230 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_sw_fini()268 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_hw_init()319 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_hw_fini()387 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_mc_resume()544 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_disable_clock_gating()709 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_enable_clock_gating()[all …]
375 adev->uvd.harvest_config |= 1 << i; in uvd_v7_0_early_init()405 if (adev->uvd.harvest_config & (1 << j)) in uvd_v7_0_sw_init()442 if (adev->uvd.harvest_config & (1 << j)) in uvd_v7_0_sw_init()503 if (adev->uvd.harvest_config & (1 << j)) in uvd_v7_0_sw_fini()533 if (adev->uvd.harvest_config & (1 << j)) in uvd_v7_0_hw_init()674 if (adev->uvd.harvest_config & (1 << i)) in uvd_v7_0_mc_resume()753 if (adev->uvd.harvest_config & (1 << i)) in uvd_v7_0_mmsch_start()811 if (adev->uvd.harvest_config & (1 << i)) in uvd_v7_0_sriov_start()956 if (adev->uvd.harvest_config & (1 << k)) in uvd_v7_0_start()970 if (adev->uvd.harvest_config & (1 << k)) in uvd_v7_0_start()[all …]
88 adev->vcn.harvest_config = 0; in vcn_v3_0_early_init()150 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_sw_init()250 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_sw_fini()292 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_hw_init()321 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_hw_init()365 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_hw_fini()1089 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_start()1307 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_start_sriov()1509 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_stop()2070 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_set_dec_ring_funcs()[all …]
51 if (adev->jpeg.harvest_config & (1 << i)) in amdgpu_jpeg_sw_fini()82 if (adev->jpeg.harvest_config & (1 << i)) in amdgpu_jpeg_idle_work_handler()
46 unsigned harvest_config; member
224 if (adev->vcn.harvest_config & (1 << i)) in amdgpu_vcn_sw_init()259 if (adev->vcn.harvest_config & (1 << j)) in amdgpu_vcn_sw_fini()318 if (adev->vcn.harvest_config & (1 << i)) in amdgpu_vcn_suspend()345 if (adev->vcn.harvest_config & (1 << i)) in amdgpu_vcn_resume()390 if (adev->vcn.harvest_config & (1 << j)) in amdgpu_vcn_idle_work_handler()965 if (adev->vcn.harvest_config & (1 << i)) in amdgpu_vcn_setup_ucode()
50 unsigned harvest_config; member
67 unsigned harvest_config; member
330 if (adev->uvd.harvest_config & (1 << j)) in amdgpu_uvd_sw_init()382 if (adev->uvd.harvest_config & (1 << j)) in amdgpu_uvd_sw_fini()445 if (adev->uvd.harvest_config & (1 << j)) in amdgpu_uvd_suspend()481 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_uvd_resume()1274 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_uvd_idle_work_handler()
456 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()476 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()489 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()501 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()516 if (adev->jpeg.harvest_config & (1 << i)) in amdgpu_hw_ip_info()866 dev_info->vce_harvest_config = adev->vce.harvest_config; in amdgpu_info_ioctl()
243 unsigned harvest_config; member
704 mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;705 mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK;936 if (adev->vce.harvest_config & (1 << i))
501 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; in amdgpu_discovery_harvest_ip()503 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; in amdgpu_discovery_harvest_ip()515 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; in amdgpu_discovery_harvest_ip()
751 if (adev->vcn.harvest_config & (1 << i)) in sienna_cichlid_set_default_dpm_table()774 if (adev->vcn.harvest_config & (1 << i)) in sienna_cichlid_set_default_dpm_table()875 if (adev->vcn.harvest_config & (1 << i)) in sienna_cichlid_dpm_set_vcn_enable()
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