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Searched refs:hcr (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/usb/serial/
A Dark3116.c67 __u32 hcr; /* handshake control register (0x8) member
145 priv->hcr = 0; in ark3116_port_probe()
200 __u8 lcr, hcr, eval; in ark3116_set_termios() local
229 hcr = (cflag & CRTSCTS) ? 0x03 : 0x00; in ark3116_set_termios()
260 __func__, hcr, lcr, quot); in ark3116_set_termios()
263 if (priv->hcr != hcr) { in ark3116_set_termios()
264 priv->hcr = hcr; in ark3116_set_termios()
265 ark3116_write_reg(serial, 0x8, hcr); in ark3116_set_termios()
/linux/arch/arm64/include/asm/
A Dhardirq.h22 u64 hcr; member
58 ___ctx->hcr = ___hcr; \
70 ___hcr = ___ctx->hcr; \
/linux/arch/arm64/kvm/hyp/include/hyp/
A Dswitch.h116 u64 hcr = vcpu->arch.hcr_el2; in ___activate_traps() local
119 hcr |= HCR_TVM; in ___activate_traps()
121 write_sysreg(hcr, hcr_el2); in ___activate_traps()
123 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE)) in ___activate_traps()
/linux/drivers/infiniband/hw/mthca/
A Dmthca_cmd.c194 return readl(dev->hcr + HCR_STATUS_OFFSET) & in go_bit()
257 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); in mthca_cmd_post_hcr()
258 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); in mthca_cmd_post_hcr()
259 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4); in mthca_cmd_post_hcr()
270 op), dev->hcr + 6 * 4); in mthca_cmd_post_hcr()
367 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 | in mthca_cmd_poll()
369 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4)); in mthca_cmd_poll()
528 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE, in mthca_cmd_init()
530 if (!dev->hcr) { in mthca_cmd_init()
539 iounmap(dev->hcr); in mthca_cmd_init()
[all …]
A Dmthca_dev.h322 void __iomem *hcr; member
/linux/drivers/net/wireless/intersil/hostap/
A Dhostap_cs.c244 static void sandisk_write_hcr(local_info_t *local, int hcr) in sandisk_write_hcr() argument
252 HFA384X_OUTB(hcr, SANDISK_HCR_OFF); in sandisk_write_hcr()
368 static void prism2_pccard_genesis_reset(local_info_t *local, int hcr) in prism2_pccard_genesis_reset() argument
378 sandisk_write_hcr(local, hcr); in prism2_pccard_genesis_reset()
399 res = pcmcia_write_config_byte(hw_priv->link, CISREG_CCSR, hcr); in prism2_pccard_genesis_reset()
A Dhostap_download.c388 static int prism2_enable_genesis(local_info_t *local, int hcr) in prism2_enable_genesis() argument
395 dev->name, hcr); in prism2_enable_genesis()
398 local->func->genesis_reset(local, hcr); in prism2_enable_genesis()
407 hcr); in prism2_enable_genesis()
411 hcr, initseq, readbuf); in prism2_enable_genesis()
A Dhostap_plx.c296 static void prism2_plx_genesis_reset(local_info_t *local, int hcr) in prism2_plx_genesis_reset() argument
306 outb(hcr, hw_priv->cor_offset + 2); in prism2_plx_genesis_reset()
316 writeb(hcr, hw_priv->attr_mem + hw_priv->cor_offset + 2); in prism2_plx_genesis_reset()
A Dhostap_pci.c267 static void prism2_pci_genesis_reset(local_info_t *local, int hcr) in prism2_pci_genesis_reset() argument
273 HFA384X_OUTW(hcr, HFA384X_PCIHCR_OFF); in prism2_pci_genesis_reset()
A Dhostap_wlan.h577 void (*genesis_reset)(local_info_t *local, int hcr);
/linux/drivers/net/ethernet/mellanox/mlx4/
A Dcmd.c437 u32 __iomem *hcr = cmd->hcr; in mlx4_cmd_post() local
496 op), hcr + 6); in mlx4_cmd_post()
581 void __iomem *hcr = priv->cmd.hcr; in mlx4_cmd_poll() local
638 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 | in mlx4_cmd_poll()
640 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4)); in mlx4_cmd_poll()
642 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24; in mlx4_cmd_poll()
2520 if (!mlx4_is_slave(dev) && !priv->cmd.hcr) { in mlx4_cmd_init()
2523 if (!priv->cmd.hcr) { in mlx4_cmd_init()
2613 if (!mlx4_is_slave(dev) && priv->cmd.hcr && in mlx4_cmd_cleanup()
2615 iounmap(priv->cmd.hcr); in mlx4_cmd_cleanup()
[all …]
A Dmlx4.h630 void __iomem *hcr; member
/linux/drivers/atm/
A Dfore200e.c467 writel(PCA200E_HCR_CLRINTR, fore200e->regs.pca.hcr); in fore200e_pca_irq_ack()
474 writel(PCA200E_HCR_RESET, fore200e->regs.pca.hcr); in fore200e_pca_reset()
476 writel(0, fore200e->regs.pca.hcr); in fore200e_pca_reset()
494 fore200e->regs.pca.hcr = fore200e->virt_base + PCA200E_HCR_OFFSET; in fore200e_pca_map()
644 u32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY; in fore200e_sba_irq_enable() local
645 fore200e->bus->write(hcr | SBA200E_HCR_INTR_ENA, fore200e->regs.sba.hcr); in fore200e_sba_irq_enable()
655 u32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY; in fore200e_sba_irq_ack() local
656 fore200e->bus->write(hcr | SBA200E_HCR_INTR_CLR, fore200e->regs.sba.hcr); in fore200e_sba_irq_ack()
661 fore200e->bus->write(SBA200E_HCR_RESET, fore200e->regs.sba.hcr); in fore200e_sba_reset()
663 fore200e->bus->write(0, fore200e->regs.sba.hcr); in fore200e_sba_reset()
[all …]
A Dfore200e.h773 volatile u32 __iomem * hcr; /* address of host control register */ member
782 u32 __iomem *hcr; /* address of host control register */ member
/linux/arch/arm64/kvm/hyp/
A Dvgic-v3-sr.c723 u32 hcr; in __vgic_v3_bump_eoicount() local
725 hcr = read_gicreg(ICH_HCR_EL2); in __vgic_v3_bump_eoicount()
726 hcr += 1 << ICH_HCR_EOIcount_SHIFT; in __vgic_v3_bump_eoicount()
727 write_gicreg(hcr, ICH_HCR_EL2); in __vgic_v3_bump_eoicount()
/linux/arch/arm64/kvm/
A Darm.c971 unsigned long *hcr; in vcpu_interrupt_line() local
978 hcr = vcpu_hcr(vcpu); in vcpu_interrupt_line()
980 set = test_and_set_bit(bit_index, hcr); in vcpu_interrupt_line()
982 set = test_and_clear_bit(bit_index, hcr); in vcpu_interrupt_line()
A Dmmu.c1605 unsigned long hcr = *vcpu_hcr(vcpu); in kvm_set_way_flush() local
1616 if (!(hcr & HCR_TVM)) { in kvm_set_way_flush()
1620 *vcpu_hcr(vcpu) = hcr | HCR_TVM; in kvm_set_way_flush()
/linux/drivers/infiniband/hw/hns/
A Dhns_roce_hw_v1.c1688 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG); in hns_roce_v1_post_mbox() local
1714 writeq(in_param, hcr + 0); in hns_roce_v1_post_mbox()
1715 writeq(out_param, hcr + 2); in hns_roce_v1_post_mbox()
1716 writel(in_modifier, hcr + 4); in hns_roce_v1_post_mbox()
1720 writel(val, hcr + 5); in hns_roce_v1_post_mbox()
1728 u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG; in hns_roce_v1_chk_mbox() local
1742 __raw_readl(hcr + HCR_STATUS_OFFSET)); in hns_roce_v1_chk_mbox()

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