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Searched refs:hws (Results 1 – 25 of 182) sorted by relevance

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/linux/drivers/clk/imx/
A Dclk-imx7d.c377 static struct clk_hw **hws; variable
391 hws = clk_hw_data->hws; in imx7d_clocks_init()
862 hws[IMX7D_ARM_A7_ROOT_CLK]->clk, in imx7d_clocks_init()
871 clk_set_parent(hws[IMX7D_PLL_ARM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ARM_MAIN]->clk); in imx7d_clocks_init()
872 clk_set_parent(hws[IMX7D_PLL_DRAM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_DRAM_MAIN]->clk); in imx7d_clocks_init()
873 clk_set_parent(hws[IMX7D_PLL_SYS_MAIN_BYPASS]->clk, hws[IMX7D_PLL_SYS_MAIN]->clk); in imx7d_clocks_init()
874 clk_set_parent(hws[IMX7D_PLL_ENET_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ENET_MAIN]->clk); in imx7d_clocks_init()
875 clk_set_parent(hws[IMX7D_PLL_AUDIO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_AUDIO_MAIN]->clk); in imx7d_clocks_init()
876 clk_set_parent(hws[IMX7D_PLL_VIDEO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_VIDEO_MAIN]->clk); in imx7d_clocks_init()
878 clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk); in imx7d_clocks_init()
[all …]
A Dclk-imx8mm.c312 hws = clk_hw_data->hws; in imx8mm_clocks_probe()
424 hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV]; in imx8mm_clocks_probe()
425 hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV]; in imx8mm_clocks_probe()
433 hws[IMX8MM_CLK_M4_SRC] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
434 hws[IMX8MM_CLK_M4_CG] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
435 hws[IMX8MM_CLK_M4_DIV] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
436 hws[IMX8MM_CLK_VPU_SRC] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
437 hws[IMX8MM_CLK_VPU_CG] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
438 hws[IMX8MM_CLK_VPU_DIV] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
440 hws[IMX8MM_CLK_GPU3D_CG] = hws[IMX8MM_CLK_GPU3D_CORE]; in imx8mm_clocks_probe()
[all …]
A Dclk-imx6sx.c85 static struct clk_hw **hws; variable
131 hws = clk_hw_data->hws; in imx6sx_clocks_init()
177 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
179 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
180 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
181 clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk); in imx6sx_clocks_init()
182 clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); in imx6sx_clocks_init()
183 clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); in imx6sx_clocks_init()
514 clk_set_parent(hws[IMX6SX_CLK_ENET_SEL]->clk, hws[IMX6SX_CLK_ENET_PODF]->clk); in imx6sx_clocks_init()
[all …]
A Dclk-imx8mq.c297 hws = clk_hw_data->hws; in imx8mq_clocks_probe()
403 hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV]; in imx8mq_clocks_probe()
404 hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV]; in imx8mq_clocks_probe()
411 hws[IMX8MQ_CLK_M4_SRC] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
412 hws[IMX8MQ_CLK_M4_CG] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
413 hws[IMX8MQ_CLK_M4_DIV] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
414 hws[IMX8MQ_CLK_VPU_SRC] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
415 hws[IMX8MQ_CLK_VPU_CG] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
416 hws[IMX8MQ_CLK_VPU_DIV] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
417 hws[IMX8MQ_CLK_GPU_CORE_SRC] = hws[IMX8MQ_CLK_GPU_CORE]; in imx8mq_clocks_probe()
[all …]
A Dclk-imx6ul.c71 static struct clk_hw **hws; variable
125 hws = clk_hw_data->hws; in imx6ul_clocks_init()
166 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
167 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
168 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
169 clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk); in imx6ul_clocks_init()
170 clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk); in imx6ul_clocks_init()
171 clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk); in imx6ul_clocks_init()
172 clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk); in imx6ul_clocks_init()
497 clk_set_parent(hws[IMX6UL_CLK_PERCLK_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk); in imx6ul_clocks_init()
[all …]
A Dclk-imx8mp.c402 static struct clk_hw **hws; variable
431 hws = clk_hw_data->hws; in imx8mp_clocks_probe()
433 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
524 hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV]; in imx8mp_clocks_probe()
525 hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV]; in imx8mp_clocks_probe()
532 hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI]; in imx8mp_clocks_probe()
706 hws[IMX8MP_CLK_A53_CORE]->clk, in imx8mp_clocks_probe()
707 hws[IMX8MP_CLK_A53_CORE]->clk, in imx8mp_clocks_probe()
708 hws[IMX8MP_ARM_PLL_OUT]->clk, in imx8mp_clocks_probe()
709 hws[IMX8MP_CLK_A53_DIV]->clk); in imx8mp_clocks_probe()
[all …]
A Dclk-imx8mn.c293 static struct clk_hw **hws; variable
308 hws = clk_hw_data->hws; in imx8mn_clocks_probe()
424 hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV]; in imx8mn_clocks_probe()
425 hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV]; in imx8mn_clocks_probe()
432 hws[IMX8MN_CLK_GPU_CORE_SRC] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
433 hws[IMX8MN_CLK_GPU_CORE_CG] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
434 hws[IMX8MN_CLK_GPU_CORE_DIV] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
435 hws[IMX8MN_CLK_GPU_SHADER_SRC] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
436 hws[IMX8MN_CLK_GPU_SHADER_CG] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
437 hws[IMX8MN_CLK_GPU_SHADER_DIV] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
[all …]
A Dclk-imx6q.c92 static struct clk_hw **hws; variable
443 hws = clk_hw_data->hws; in imx6q_clocks_init()
494 clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); in imx6q_clocks_init()
495 clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); in imx6q_clocks_init()
496 clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); in imx6q_clocks_init()
497 clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); in imx6q_clocks_init()
498 clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); in imx6q_clocks_init()
499 clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk); in imx6q_clocks_init()
500 clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk); in imx6q_clocks_init()
909 hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER]; in imx6q_clocks_init()
[all …]
A Dclk-imx6sl.c100 static struct clk_hw **hws; variable
194 hws = clk_hw_data->hws; in imx6sl_clocks_init()
234 clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk); in imx6sl_clocks_init()
235 clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk); in imx6sl_clocks_init()
236 clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk); in imx6sl_clocks_init()
237 clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk); in imx6sl_clocks_init()
238 clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk); in imx6sl_clocks_init()
239 clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk); in imx6sl_clocks_init()
240 clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk); in imx6sl_clocks_init()
418 imx_check_clk_hws(hws, IMX6SL_CLK_END); in imx6sl_clocks_init()
[all …]
A Dclk-imx6sll.c56 static struct clk_hw **hws; variable
84 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6sll_clocks_init()
90 hws = clk_hw_data->hws; in imx6sll_clocks_init()
92 hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sll_clocks_init()
339 imx_check_clk_hws(hws, IMX6SLL_CLK_END); in imx6sll_clocks_init()
346 clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 99000000); in imx6sll_clocks_init()
349 clk_set_parent(hws[IMX6SLL_CLK_PERIPH_CLK2_SEL]->clk, hws[IMX6SLL_CLK_PLL3_USB_OTG]->clk); in imx6sll_clocks_init()
350 clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_CLK2]->clk); in imx6sll_clocks_init()
351 clk_set_parent(hws[IMX6SLL_CLK_PERIPH_PRE]->clk, hws[IMX6SLL_CLK_PLL2_BUS]->clk); in imx6sll_clocks_init()
352 clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_PRE]->clk); in imx6sll_clocks_init()
[all …]
A Dclk-imx7ulp.c49 struct clk_hw **hws; in imx7ulp_clk_scg1_init() local
58 hws = clk_data->hws; in imx7ulp_clk_scg1_init()
111 …hws[IMX7ULP_CLK_CORE] = imx_clk_hw_cpu("core", "divcore", hws[IMX7ULP_CLK_CORE_DIV]->clk, hws[IMX… in imx7ulp_clk_scg1_init()
113 …hws[IMX7ULP_CLK_HSRUN_CORE] = imx_clk_hw_cpu("hsrun_core", "hsrun_divcore", hws[IMX7ULP_CLK_HSRUN_… in imx7ulp_clk_scg1_init()
129 imx_check_clk_hws(hws, clk_data->num); in imx7ulp_clk_scg1_init()
138 struct clk_hw **hws; in imx7ulp_clk_pcc2_init() local
147 hws = clk_data->hws; in imx7ulp_clk_pcc2_init()
186 struct clk_hw **hws; in imx7ulp_clk_pcc3_init() local
195 hws = clk_data->hws; in imx7ulp_clk_pcc3_init()
233 struct clk_hw **hws; in imx7ulp_clk_smc1_init() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_hwseq.c32 hws->ctx
34 hws->regs->reg
38 hws->shifts->field_name, hws->masks->field_name
40 void dce_enable_fe_clock(struct dce_hwseq *hws, in dce_enable_fe_clock() argument
53 struct dce_hwseq *hws = dc->hwseq; in dce_pipe_control_lock() local
75 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) in dce_pipe_control_lock()
80 if (hws->wa.blnd_crtc_trigger) { in dce_pipe_control_lock()
97 void dce_set_blender_mode(struct dce_hwseq *hws, in dce_set_blender_mode() argument
129 if (hws->masks->BLND_ALPHA_MODE != 0) { in dce_set_blender_mode()
170 dce_disable_sram_shut_down(hws); in dce_clock_gating_power_up()
[all …]
/linux/drivers/clk/x86/
A Dclk-fch.c34 static struct clk_hw *hws[ST_MAX_CLKS]; variable
45 hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", in fch_clk_probe()
47 hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", in fch_clk_probe()
50 hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux", in fch_clk_probe()
55 clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk); in fch_clk_probe()
57 hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", in fch_clk_probe()
61 devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], in fch_clk_probe()
64 hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", in fch_clk_probe()
67 hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", in fch_clk_probe()
71 devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE], in fch_clk_probe()
[all …]
/linux/drivers/clk/
A Dclk-clps711x.c106 clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] = in clps711x_clk_init_dt()
108 clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] = in clps711x_clk_init_dt()
110 clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] = in clps711x_clk_init_dt()
112 clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] = in clps711x_clk_init_dt()
116 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] = in clps711x_clk_init_dt()
120 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] = in clps711x_clk_init_dt()
124 clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] = in clps711x_clk_init_dt()
128 clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] = in clps711x_clk_init_dt()
132 clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] = in clps711x_clk_init_dt()
134 clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] = in clps711x_clk_init_dt()
[all …]
A Dclk-ast2600.c484 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw; in aspeed_g6_clk_probe()
495 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw; in aspeed_g6_clk_probe()
525 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; in aspeed_g6_clk_probe()
539 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; in aspeed_g6_clk_probe()
631 aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw; in aspeed_g6_clk_probe()
640 aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw; in aspeed_g6_clk_probe()
649 aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw; in aspeed_g6_clk_probe()
671 aspeed_g6_clk_data->hws[i] = hw; in aspeed_g6_clk_probe()
758 aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw; in aspeed_g6_cc()
764 aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw; in aspeed_g6_cc()
[all …]
A Dclk-aspeed.c431 aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; in aspeed_clk_probe()
441 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; in aspeed_clk_probe()
455 aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; in aspeed_clk_probe()
464 aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; in aspeed_clk_probe()
506 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; in aspeed_clk_probe()
513 aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; in aspeed_clk_probe()
561 aspeed_clk_data->hws[i] = hw; in aspeed_clk_probe()
641 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; in aspeed_ast2400_cc()
648 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; in aspeed_ast2400_cc()
678 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; in aspeed_ast2500_cc()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_hwseq.c58 hws->ctx
60 hws->regs->reg
67 hws->shifts->field_name, hws->masks->field_name
71 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power() local
111 struct dce_hwseq *hws = dc->hwseq; in dcn31_init_hw() local
137 hws->funcs.enable_power_gating_plane(hws, true); in dcn31_init_hw()
143 hws->funcs.bios_golden_init(dc); in dcn31_init_hw()
198 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); in dcn31_init_hw()
279 hws->funcs.setup_hpo_hw_control(hws, false); in dcn31_init_hw()
311 struct dce_hwseq *hws, in dcn31_dsc_pg_control() argument
[all …]
/linux/drivers/isdn/hardware/mISDN/
A Diohelper.h27 struct hws *hw = p; \
31 struct hws *hw = p; \
35 struct hws *hw = p; \
39 struct hws *hw = p; \
45 struct hws *hw = p; \
50 struct hws *hw = p; \
55 struct hws *hw = p; \
60 struct hws *hw = p; \
67 struct hws *hw = p; \
71 struct hws *hw = p; \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_hwseq.c18 hws->ctx
20 hws->regs->reg
24 hws->shifts->field_name, hws->masks->field_name
27 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn303_dpp_pg_control() argument
32 void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) in dcn303_hubp_pg_control() argument
37 void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) in dcn303_dsc_pg_control() argument
42 void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) in dcn303_enable_power_gating_plane() argument
/linux/drivers/gpu/drm/i915/selftests/
A Digt_spinner.c21 if (IS_ERR(spin->hws)) { in igt_spinner_init()
22 err = PTR_ERR(spin->hws); in igt_spinner_init()
36 i915_gem_object_put(spin->hws); in igt_spinner_init()
144 struct i915_vma *hws, *vma; in igt_spinner_create_request() local
160 hws = spin->hws_vma; in igt_spinner_create_request()
171 err = move_to_active(hws, rq, 0); in igt_spinner_create_request()
184 *batch++ = hws_address(hws, rq); in igt_spinner_create_request()
188 *batch++ = hws_address(hws, rq); in igt_spinner_create_request()
191 *batch++ = hws_address(hws, rq); in igt_spinner_create_request()
260 i915_gem_object_unpin_map(spin->hws); in igt_spinner_fini()
[all …]
/linux/drivers/clk/bcm/
A Dclk-bcm2711-dvp.c38 struct_size(dvp->data, hws, NR_CLOCKS), in clk_dvp_probe()
59 data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev, in clk_dvp_probe()
65 if (IS_ERR(data->hws[0])) in clk_dvp_probe()
66 return PTR_ERR(data->hws[0]); in clk_dvp_probe()
68 data->hws[1] = clk_hw_register_gate_parent_data(&pdev->dev, in clk_dvp_probe()
74 if (IS_ERR(data->hws[1])) { in clk_dvp_probe()
75 ret = PTR_ERR(data->hws[1]); in clk_dvp_probe()
88 clk_hw_unregister_gate(data->hws[1]); in clk_dvp_probe()
91 clk_hw_unregister_gate(data->hws[0]); in clk_dvp_probe()
100 clk_hw_unregister_gate(data->hws[1]); in clk_dvp_remove()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_hwseq.c44 hws->ctx
47 hws->regs->reg
54 hws->shifts->field_name, hws->masks->field_name
209 hws->fb_base.low_part = fb_base; in read_mmhub_vm_setup()
210 hws->fb_base.quad_part <<= 24; in read_mmhub_vm_setup()
212 hws->fb_top.low_part = fb_top; in read_mmhub_vm_setup()
213 hws->fb_top.quad_part <<= 24; in read_mmhub_vm_setup()
217 hws->uma_top.quad_part = hws->fb_top.quad_part in read_mmhub_vm_setup()
218 - hws->fb_base.quad_part + hws->fb_offset.quad_part; in read_mmhub_vm_setup()
238 hws->funcs.dccg_init(hws); in dcn201_init_hw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_hwseq.c36 hws->ctx
38 hws->regs->reg
42 hws->shifts->field_name, hws->masks->field_name
45 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn302_dpp_pg_control() argument
50 if (hws->ctx->dc->debug.disable_dpp_power_gate) in dcn302_dpp_pg_control()
102 void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) in dcn302_hubp_pg_control() argument
107 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn302_hubp_pg_control()
159 void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) in dcn302_dsc_pg_control() argument
165 if (hws->ctx->dc->debug.disable_dsc_power_gate) in dcn302_dsc_pg_control()
/linux/drivers/clk/imgtec/
A Dclk-boston.c61 onecell = kzalloc(struct_size(onecell, hws, BOSTON_CLK_COUNT), in clk_boston_setup()
73 onecell->hws[BOSTON_CLK_INPUT] = hw; in clk_boston_setup()
80 onecell->hws[BOSTON_CLK_SYS] = hw; in clk_boston_setup()
87 onecell->hws[BOSTON_CLK_CPU] = hw; in clk_boston_setup()
98 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_CPU]); in clk_boston_setup()
100 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_SYS]); in clk_boston_setup()
102 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_INPUT]); in clk_boston_setup()
/linux/drivers/clk/xilinx/
A Dxlnx_vcu.c526 struct clk_hw **hws; in xvcu_register_clock_provider() local
534 hws = data->hws; in xvcu_register_clock_provider()
553 hws[CLK_XVCU_ENC_CORE] = in xvcu_register_clock_provider()
558 hws[CLK_XVCU_ENC_MCU] = in xvcu_register_clock_provider()
563 hws[CLK_XVCU_DEC_CORE] = in xvcu_register_clock_provider()
568 hws[CLK_XVCU_DEC_MCU] = in xvcu_register_clock_provider()
580 struct clk_hw **hws = data->hws; in xvcu_unregister_clock_provider() local
582 if (!IS_ERR_OR_NULL(hws[CLK_XVCU_DEC_MCU])) in xvcu_unregister_clock_provider()
584 if (!IS_ERR_OR_NULL(hws[CLK_XVCU_DEC_CORE])) in xvcu_unregister_clock_provider()
586 if (!IS_ERR_OR_NULL(hws[CLK_XVCU_ENC_MCU])) in xvcu_unregister_clock_provider()
[all …]

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