Home
last modified time | relevance | path

Searched refs:i0 (Results 1 – 25 of 63) sorted by relevance

123

/linux/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5.xml.h277 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W() argument
279 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W_REG() argument
299 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R() argument
301 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R_REG() argument
372 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } in REG_MDP5_CTL() argument
452 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); } in REG_MDP5_CTL_OP() argument
1087 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } in REG_MDP5_LM() argument
1280 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } in REG_MDP5_DSPP() argument
1325 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } in REG_MDP5_PP() argument
1416 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } in REG_MDP5_WB() argument
[all …]
/linux/drivers/gpu/drm/msm/disp/mdp4/
A Dmdp4.xml.h327 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP() argument
329 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG() argument
331 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE() argument
345 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE() argument
420 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CSC() argument
445 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } in REG_MDP4_LUTN() argument
453 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } in REG_MDP4_DMA_E_QUANT() argument
464 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } in REG_MDP4_DMA() argument
598 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } in REG_MDP4_PIPE() argument
826 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } in REG_MDP4_PIPE_CSC() argument
[all …]
/linux/drivers/gpu/drm/msm/dsi/
A Ddsi_phy_14nm.xml.h118 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_14nm_PHY_LN() argument
120 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG0() argument
128 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG1() argument
131 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG2() argument
133 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG3() argument
135 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TEST_DATAPATH() argument
137 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_TEST_STR() argument
139 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_4() argument
147 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_5() argument
155 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_6() argument
[all …]
A Ddsi_phy_10nm.xml.h127 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_10nm_PHY_LN() argument
129 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG0() argument
131 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG1() argument
133 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG2() argument
135 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG3() argument
137 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0… in REG_DSI_10nm_PHY_LN_TEST_DATAPATH() argument
139 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_PIN_SWAP() argument
141 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0… in REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL() argument
147 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0… in REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL() argument
149 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_LPRX_CTRL() argument
[all …]
A Ddsi_phy_20nm.xml.h57 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_20nm_PHY_LN() argument
59 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_0() argument
61 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_1() argument
63 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_2() argument
65 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_3() argument
67 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_4() argument
69 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0… in REG_DSI_20nm_PHY_LN_TEST_DATAPATH() argument
71 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_DEBUG_SEL() argument
73 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } in REG_DSI_20nm_PHY_LN_TEST_STR_0() argument
75 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_TEST_STR_1() argument
A Ddsi_phy_28nm.xml.h57 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN() argument
59 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_0() argument
61 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_1() argument
63 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_2() argument
65 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_3() argument
67 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_4() argument
69 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0… in REG_DSI_28nm_PHY_LN_TEST_DATAPATH() argument
71 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_DEBUG_SEL() argument
73 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_0() argument
75 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_1() argument
A Ddsi_phy_5nm.xml.h157 static inline uint32_t REG_DSI_5nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_5nm_PHY_LN() argument
159 static inline uint32_t REG_DSI_5nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_5nm_PHY_LN_CFG0() argument
161 static inline uint32_t REG_DSI_5nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_5nm_PHY_LN_CFG1() argument
163 static inline uint32_t REG_DSI_5nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_5nm_PHY_LN_CFG2() argument
165 static inline uint32_t REG_DSI_5nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0;… in REG_DSI_5nm_PHY_LN_TEST_DATAPATH() argument
167 static inline uint32_t REG_DSI_5nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; } in REG_DSI_5nm_PHY_LN_PIN_SWAP() argument
169 static inline uint32_t REG_DSI_5nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_5nm_PHY_LN_LPRX_CTRL() argument
171 static inline uint32_t REG_DSI_5nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } in REG_DSI_5nm_PHY_LN_TX_DCTRL() argument
A Ddsi_phy_7nm.xml.h159 static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_7nm_PHY_LN() argument
161 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_CFG0() argument
163 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_CFG1() argument
165 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_CFG2() argument
167 static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0;… in REG_DSI_7nm_PHY_LN_TEST_DATAPATH() argument
169 static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_PIN_SWAP() argument
171 static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_LPRX_CTRL() argument
173 static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_TX_DCTRL() argument
A Ddsi_phy_28nm_8960.xml.h57 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN() argument
59 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0() argument
61 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1() argument
63 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2() argument
65 …nline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH() argument
67 …c inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0() argument
69 …c inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1() argument
A Dmmss_cc.xml.h72 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0);… in REG_MMSS_CC_CLK() argument
74 …tic inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_CC() argument
91 …tic inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_MD() argument
105 …tic inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_NS() argument
/linux/drivers/gpu/drm/etnaviv/
A Dstate.xml.h73 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) argument
192 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) argument
198 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) argument
200 #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) argument
210 #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) argument
214 #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) argument
315 #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0)) argument
412 #define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0)) argument
416 #define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0)) argument
446 #define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) argument
[all …]
/linux/arch/sparc/lib/
A Ddivdi3.S49 sub %i0,%o4,%i0 ! this kills msb of n
50 addx %i0,%i0,%i0 ! so this cannot give carry
57 sub %i0,%o4,%i0 ! this kills msb of n
58 4: sub %i0,%o4,%i0
59 5: addxcc %i0,%i0,%i0
65 sub %i0,%o4,%i0
109 sub %i0,%o4,%i0 ! this kills msb of n
110 addx %i0,%i0,%i0 ! so this cannot give carry
118 4: sub %i0,%o4,%i0
119 5: addxcc %i0,%i0,%i0
[all …]
A Dudivdi3.S25 sub %i0,%o3,%i0 ! this kills msb of n
26 addx %i0,%i0,%i0 ! so this cannot give carry
34 4: sub %i0,%o3,%i0
35 5: addxcc %i0,%i0,%i0
41 sub %i0,%o3,%i0
90 addx %i0,%i0,%i0 ! so this cannot give carry
98 4: sub %i0,%o3,%i0
99 5: addxcc %i0,%i0,%i0
105 sub %i0,%o3,%i0
157 sll %i0,%o2,%i0
[all …]
A Dxor.S262 sub %i0, 64, %i0
305 subcc %i0, 64, %i0
364 srlx %i0, 6, %g1
365 mov %i1, %i0
393 add %i0, 0x40, %i0
412 mov %i1, %i0
454 add %i0, 0x40, %i0
475 mov %i1, %i0
536 add %i0, 0x40, %i0
559 mov %i1, %i0
[all …]
A DNGpage.S33 stxa %o2, [%i0 + 0x00] %asi
34 stxa %o3, [%i0 + 0x08] %asi
35 stxa %o4, [%i0 + 0x10] %asi
36 stxa %o5, [%i0 + 0x18] %asi
37 stxa %l2, [%i0 + 0x20] %asi
38 stxa %l3, [%i0 + 0x28] %asi
39 stxa %l4, [%i0 + 0x30] %asi
40 stxa %l5, [%i0 + 0x38] %asi
45 stxa %o2, [%i0 + 0x40] %asi
46 stxa %o3, [%i0 + 0x48] %asi
[all …]
A Dmemcpy.S305 stb %g5, [%i0]
308 add %i0, 1, %i0
312 stb %g3, [%i0]
315 add %i0, 2, %i0
334 add %i0, -8, %i0
340 add %i0, -12, %i0
347 add %i0, -4, %i0
366 st %g2, [%i0]
387 add %i0, 16, %i0
397 st %g2, [%i0]
[all …]
A DNGmemcpy.S88 add %i2, %i5, %i0
92 add %i2, %g1, %i0
97 add %i2, %g1, %i0
102 add %i2, %g1, %i0
107 add %i2, %g1, %i0
112 add %i2, %g1, %i0
140 add %i2, 8, %i0
144 add %i2, 4, %i0
148 add %i2, 1, %i0
157 mov %i2, %i0
[all …]
/linux/arch/arm64/crypto/
A Daes-ce.S58 aes\de \i0\().16b, \k\().16b
59 aes\mc \i0\().16b, \i0\().16b
77 .macro round_Nx, enc, k, i0, i1, i2, i3, i4
79 do_enc_Nx e, mc, \k, \i0, \i1, \i2, \i3, \i4
87 aes\de \i0\().16b, \k\().16b
98 eor \i0\().16b, \i0\().16b, \k2\().16b
116 round_Nx \enc, v17, \i0, \i1, \i2, \i3, \i4
117 round_Nx \enc, v18, \i0, \i1, \i2, \i3, \i4
119 round_Nx \enc, v20, \i0, \i1, \i2, \i3, \i4
131 do_block_Nx e, \rounds, \i0, \i1, \i2, \i3
[all …]
/linux/drivers/gpu/drm/msm/adreno/
A Da4xx.xml.h970 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT() argument
972 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL() argument
1023 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } in REG_A4XX_RB_MRT_BASE() argument
2194 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } in REG_A4XX_CP_PROTECT() argument
2256 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } in REG_A4XX_CP_SCRATCH() argument
2366 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } in REG_A4XX_SP_VS_OUT() argument
2534 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } in REG_A4XX_SP_FS_MRT() argument
2602 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } in REG_A4XX_SP_DS_OUT() argument
2700 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } in REG_A4XX_SP_GS_OUT() argument
2994 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } in REG_A4XX_VFD_FETCH() argument
[all …]
A Da6xx.xml.h1071 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH() argument
1075 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT() argument
2007 static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; } in REG_A6XX_VSC_STATE() argument
3113 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } in REG_A6XX_RB_MRT() argument
4183 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } in REG_A6XX_VPC_VAR() argument
4232 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } in REG_A6XX_VPC_SO() argument
4853 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } in REG_A6XX_VFD_FETCH() argument
4967 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } in REG_A6XX_SP_VS_OUT() argument
5255 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } in REG_A6XX_SP_DS_OUT() argument
5435 static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; } in REG_A6XX_SP_GS_OUT() argument
[all …]
A Da5xx.xml.h1033 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } in REG_A5XX_CP_SCRATCH() argument
1035 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } in REG_A5XX_CP_SCRATCH_REG() argument
1037 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } in REG_A5XX_CP_PROTECT() argument
1039 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } in REG_A5XX_CP_PROTECT_REG() argument
3241 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; } in REG_A5XX_RB_MRT() argument
3817 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; } in REG_A5XX_VPC_VAR() argument
3900 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } in REG_A5XX_VPC_SO() argument
4059 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; } in REG_A5XX_VFD_FETCH() argument
4069 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; } in REG_A5XX_VFD_DECODE() argument
4246 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; } in REG_A5XX_SP_VS_OUT() argument
[all …]
A Da3xx.xml.h915 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT() argument
917 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT_REG() argument
1221 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT() argument
1223 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT_CONTROL() argument
1246 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } in REG_A3XX_RB_MRT_BUF_INFO() argument
1968 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } in REG_A3XX_VFD_FETCH() argument
2000 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } in REG_A3XX_VFD_DECODE() argument
2395 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } in REG_A3XX_SP_VS_OUT() argument
2397 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } in REG_A3XX_SP_VS_OUT_REG() argument
2668 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } in REG_A3XX_SP_FS_MRT() argument
[all …]
/linux/fs/jffs2/
A Dcompr_rubin.c105 long i0, i1; in encode() local
120 if (i0 <= 0) in encode()
121 i0 = 1; in encode()
123 if (i0 >= rs->p) in encode()
129 rs->p = i0; in encode()
132 rs->q += i0; in encode()
210 if (i0 <= 0) in decode()
211 i0 = 1; in decode()
219 rs->q += i0; in decode()
220 i0 = rs->p - i0; in decode()
[all …]
/linux/drivers/gpu/drm/msm/hdmi/
A Dhdmi.xml.h179 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } in REG_HDMI_AVI_INFO() argument
183 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } in REG_HDMI_GENERIC0() argument
187 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } in REG_HDMI_GENERIC1() argument
189 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR() argument
191 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR_0() argument
199 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } in REG_HDMI_ACR_1() argument
396 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION() argument
398 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION_REG() argument
/linux/tools/testing/selftests/proc/
A Dproc-uptime-001.c28 uint64_t start, u0, u1, i0, i1; in main() local
34 proc_uptime(fd, &u0, &i0); in main()
39 assert(i1 >= i0); in main()
41 i0 = i1; in main()

Completed in 169 milliseconds

123