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Searched refs:i915_ggtt_offset (Results 1 – 25 of 33) sorted by relevance

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/linux/drivers/gpu/drm/i915/gt/
A Dintel_lrc.c786 const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); in init_wa_bb_regs()
795 i915_ggtt_offset(wa_ctx->vma) + in init_wa_bb_regs()
1106 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_timestamp_wa()
1134 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_restore_scratch()
1150 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_cmd_buf_wa()
1214 i915_ggtt_offset(ce->state) + in setup_indirect_ctx_bb()
1266 return i915_ggtt_offset(ce->state) | desc; in lrc_descriptor()
1279 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma); in lrc_update_regs()
1322 if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) { in lrc_check_regs()
1326 i915_ggtt_offset(ring->vma)); in lrc_check_regs()
[all …]
A Dselftest_lrc.c76 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
401 *cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32); in __live_lrc_state()
404 expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma); in __live_lrc_state()
408 *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32); in __live_lrc_state()
525 i915_ggtt_offset(ce->engine->status_page.vma) + in __gpr_read()
556 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in __gpr_read()
702 i915_ggtt_offset(ce->engine->status_page.vma) + in create_timestamp()
1050 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in record_registers()
1170 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in poison_registers()
1483 *cs++ = i915_ggtt_offset(ce->state) + in emit_indirect_ctx_bb_canary()
A Dintel_timeline.c206 i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_pin()
314 tl->hwsp_offset = i915_ggtt_offset(tl->hwsp_ggtt) + next_ofs; in __intel_timeline_get_seqno()
351 *hwsp = i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_read_hwsp()
A Dintel_context_sseu.c26 offset = i915_ggtt_offset(ce->state) + in gen8_emit_rpcs_config()
A Dintel_gt.h63 return i915_ggtt_offset(gt->scratch) + field; in intel_gt_scratch_offset()
A Dselftest_mocs.c237 offset = i915_ggtt_offset(vma); in check_mocs_engine()
242 offset -= i915_ggtt_offset(vma); in check_mocs_engine()
A Dintel_ring_submission.c129 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
213 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
261 i915_ggtt_offset(ring->vma)); in xcs_resume()
747 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context()
754 *cs++ = i915_ggtt_offset(ce->state) | flags; in mi_set_context()
A Dselftest_timeline.c848 w->addr = i915_ggtt_offset(vma); in setup_watcher()
883 w->addr = i915_ggtt_offset(w->vma); in create_watcher()
897 GEM_BUG_ON(w->addr - i915_ggtt_offset(w->vma) > w->vma->size); in check_watcher()
910 end = (w->addr - i915_ggtt_offset(w->vma)) / sizeof(*w->map); in check_watcher()
A Dintel_renderstate.c87 so->batch_offset = i915_ggtt_offset(so->vma); in render_state_setup()
A Dselftest_execlists.c836 *cs++ = i915_ggtt_offset(vma) + 4 * idx; in emit_semaphore_chain()
841 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in emit_semaphore_chain()
910 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in release_queue()
1055 i915_ggtt_offset(ce->engine->status_page.vma) + in create_rewinder()
1617 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
1628 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
1667 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
3230 *cs++ = i915_ggtt_offset(global); in preempt_user()
4253 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in preserved_virtual_engine()
A Dselftest_engine_pm.c76 u32 offset = i915_ggtt_offset(engine->status_page.vma); in __measure_timestamps()
A Dintel_context.c262 i915_ggtt_offset(ce->ring->vma), in __intel_context_do_pin_ww()
A Dgen6_ppgtt.c297 u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE; in pd_vma_bind()
A Dgen8_engine_cs.c334 return (i915_ggtt_offset(engine->status_page.vma) + in preempt_address()
A Dintel_engine_cs.c1480 i915_ggtt_offset(rq->ring->vma), in print_ring()
1763 i915_ggtt_offset(rq->ring->vma)); in engine_dump_request()
/linux/drivers/gpu/drm/i915/display/
A Dintel_dsb.c225 i915_ggtt_offset(dsb->vma)); in intel_dsb_commit()
239 i915_ggtt_offset(dsb->vma), tail); in intel_dsb_commit()
241 i915_ggtt_offset(dsb->vma) + tail); in intel_dsb_commit()
A Dintel_overlay.c846 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y); in intel_overlay_do_put_image()
863 iowrite32(i915_ggtt_offset(vma) + params->offset_U, in intel_overlay_do_put_image()
865 iowrite32(i915_ggtt_offset(vma) + params->offset_V, in intel_overlay_do_put_image()
1359 overlay->flip_addr = i915_ggtt_offset(vma); in get_registers()
A Dintel_fbdev.c291 i915_ggtt_offset(vma)); in intelfb_create()
/linux/drivers/gpu/drm/i915/gem/selftests/
A Di915_gem_coherency.c226 *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
227 *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
232 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
236 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
/linux/drivers/gpu/drm/i915/selftests/
A Di915_perf.c239 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_delay()
346 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_gpr()
372 *cs++ = i915_ggtt_offset(rq->engine->status_page.vma) + in live_noa_gpr()
/linux/drivers/gpu/drm/i915/
A Di915_perf.c458 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in oa_buffer_check_unlocked()
648 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_append_oa_reports()
941 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_append_oa_reports()
1252 stream->specific_ctx_id = i915_ggtt_offset(ce->state); in oa_get_render_ctx_id()
1402 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_init_oa_buffer()
1448 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_init_oa_buffer()
1502 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen12_init_oa_buffer()
1746 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4; in alloc_noa_wait()
1783 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4; in alloc_noa_wait()
1906 *cs++ = i915_ggtt_offset(stream->noa_wait); in alloc_oa_config_buffer()
[all …]
A Di915_vma.h128 static inline u32 i915_ggtt_offset(const struct i915_vma *vma) in i915_ggtt_offset() function
/linux/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc.h264 u32 offset = i915_ggtt_offset(vma); in intel_guc_ggtt_offset()
A Dintel_guc_submission.c1945 desc->process_desc = i915_ggtt_offset(ce->state) + in guc_lrc_desc_pin()
1947 desc->wq_addr = i915_ggtt_offset(ce->state) + in guc_lrc_desc_pin()
2034 if (i915_ggtt_offset(ce->state) != in __guc_context_pin()
3253 i915_ggtt_offset(engine->status_page.vma)); in setup_hwsp()
3963 return i915_ggtt_offset(ce->state) + in get_children_go_addr()
3973 return i915_ggtt_offset(ce->state) + in get_children_join_addr()
/linux/drivers/gpu/drm/i915/gvt/
A Dscheduler.c567 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma); in prepare_shadow_batch_buffer()
640 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma); in prepare_shadow_wa_ctx()

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