Searched refs:input_reg (Results 1 – 15 of 15) sorted by relevance
| /linux/drivers/pinctrl/freescale/ |
| A D | pinctrl-imx.c | 218 val = readl(ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
221 writel(val, ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
222 } else if (pin_mmio->input_reg) { in imx_pmx_set_one_pin_mmio()
229 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
232 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
235 pin_mmio->input_reg, pin_mmio->input_val); in imx_pmx_set_one_pin_mmio()
545 pin_mmio->input_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
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| A D | pinctrl-imx.h | 32 u16 input_reg; member
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| A D | fsl,imx8ulp-pinctrl.yaml | 35 setting for one pin. The first 4 integers <mux_config_reg input_reg
46 "input_reg" indicates the offset of select input register.
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| A D | fsl,imx8mm-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
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| A D | fsl,imx8mn-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
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| A D | fsl,imx8mp-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
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| A D | fsl,imx8mq-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
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| A D | fsl,imx6sx-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| A D | fsl,imx6sll-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| A D | fsl,imx6ul-pinctrl.txt | 10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| A D | fsl,imx7ulp-pinctrl.txt | 17 <mux_conf_reg input_reg mux_mode input_val> are specified
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| A D | fsl,imx7d-pinctrl.txt | 32 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| A D | fsl,imx-pinctrl.txt | 26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| /linux/drivers/pinctrl/mvebu/ |
| A D | pinctrl-armada-37xx.c | 1070 u32 mask, *irq_pol, input_reg, virq, type, level; in armada_3700_pinctrl_resume() local
1075 input_reg = INPUT_VAL; in armada_3700_pinctrl_resume()
1079 input_reg = INPUT_VAL + sizeof(u32); in armada_3700_pinctrl_resume()
1095 regmap_read(info->regmap, input_reg, &level); in armada_3700_pinctrl_resume()
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| /linux/drivers/input/touchscreen/ |
| A D | iqs5xx.c | 901 bool input_reg = !iqs5xx->input; in fw_file_store() local
925 if (input_reg) { in fw_file_store()
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