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Searched refs:io_base (Results 1 – 25 of 167) sorted by relevance

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/linux/drivers/staging/vt6655/
A Dmac.c153 io_base + MAC_REG_TEST); in MACvSetLoopbackMode()
176 MACvSelectPage1(io_base); in MACvSaveContext()
182 MACvSelectPage0(io_base); in MACvSaveContext()
203 MACvSelectPage1(io_base); in MACvRestoreContext()
208 MACvSelectPage0(io_base); in MACvRestoreContext()
226 io_base + MAC_REG_TXDMAPTR0); in MACvRestoreContext()
228 io_base + MAC_REG_AC0DMAPTR); in MACvRestoreContext()
230 io_base + MAC_REG_BCNDMAPTR); in MACvRestoreContext()
232 io_base + MAC_REG_RXDMAPTR0); in MACvRestoreContext()
462 MACvIntDisable(io_base); in MACbShutdown()
[all …]
/linux/drivers/gpu/drm/meson/
A Dmeson_viu.c130 priv->io_base + in meson_viu_set_osd_matrix()
133 priv->io_base + in meson_viu_set_osd_matrix()
136 priv->io_base + in meson_viu_set_osd_matrix()
204 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
207 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
211 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
215 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
218 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
231 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
234 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
[all …]
A Dmeson_crtc.c272 priv->io_base + in meson_g12a_crtc_enable_osd1()
275 priv->io_base + in meson_g12a_crtc_enable_osd1()
278 priv->io_base + in meson_g12a_crtc_enable_osd1()
281 priv->io_base + in meson_g12a_crtc_enable_osd1()
396 priv->io_base + in meson_crtc_irq()
399 priv->io_base + in meson_crtc_irq()
402 priv->io_base + in meson_crtc_irq()
405 priv->io_base + in meson_crtc_irq()
408 priv->io_base + in meson_crtc_irq()
411 priv->io_base + in meson_crtc_irq()
[all …]
A Dmeson_venc.c1105 priv->io_base + _REG(ENCI_VIDEO_SCH)); in meson_venc_hdmi_mode_set()
1112 priv->io_base + _REG(ENCI_YC_DELAY)); in meson_venc_hdmi_mode_set()
1166 priv->io_base + _REG(ENCI_DE_H_END)); in meson_venc_hdmi_mode_set()
1238 writel_relaxed(hs_begin, priv->io_base in meson_venc_hdmi_mode_set()
1247 writel_relaxed(hs_begin, priv->io_base in meson_venc_hdmi_mode_set()
1331 priv->io_base in meson_venc_hdmi_mode_set()
1413 priv->io_base + _REG(ENCP_DE_H_END)); in meson_venc_hdmi_mode_set()
1432 readl_relaxed(priv->io_base + in meson_venc_hdmi_mode_set()
1719 priv->io_base + _REG(ENCI_VIDEO_SAT)); in meson_venci_cvbs_mode_set()
1725 priv->io_base + _REG(ENCI_VIDEO_HUE)); in meson_venci_cvbs_mode_set()
[all …]
A Dmeson_vpp.c63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
88 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
98 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpp_init()
102 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
112 priv->io_base + _REG(VPP_OFIFO_SIZE)); in meson_vpp_init()
119 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
123 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
129 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
146 priv->io_base + _REG(VPP_SC_MISC)); in meson_vpp_init()
[all …]
A Dmeson_osd_afbcd.c90 priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
91 writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
100 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_enable()
108 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_disable()
134 priv->io_base + _REG(OSD1_AFBCD_SIZE_IN)); in meson_gxm_afbcd_setup()
137 priv->io_base + _REG(OSD1_AFBCD_HDR_PTR)); in meson_gxm_afbcd_setup()
139 priv->io_base + _REG(OSD1_AFBCD_FRAME_PTR)); in meson_gxm_afbcd_setup()
142 priv->io_base + _REG(OSD1_AFBCD_CHROMA_PTR)); in meson_gxm_afbcd_setup()
158 priv->io_base + _REG(OSD1_AFBCD_CONV_CTRL)); in meson_gxm_afbcd_setup()
284 priv->io_base + _REG(MALI_AFBCD_TOP_CTRL)); in meson_g12a_afbcd_init()
[all …]
/linux/arch/powerpc/platforms/embedded6xx/
A Dflipper-pic.c52 clrbits32(io_base + FLIPPER_IMR, mask); in flipper_pic_mask_and_ack()
54 out_be32(io_base + FLIPPER_ICR, mask); in flipper_pic_mask_and_ack()
128 void __iomem *io_base; in flipper_pic_init() local
150 __flipper_quiesce(io_base); in flipper_pic_init()
153 &flipper_irq_domain_ops, io_base); in flipper_pic_init()
170 in_be32(io_base + FLIPPER_IMR); in flipper_pic_get_irq()
213 __flipper_quiesce(io_base); in flipper_quiesce()
221 void __iomem *io_base; in flipper_platform_reset() local
225 out_8(io_base + FLIPPER_RESET, 0x00); in flipper_platform_reset()
234 void __iomem *io_base; in flipper_is_reset_button_pressed() local
[all …]
A Dhlwd-pic.c48 clrbits32(io_base + HW_BROADWAY_IMR, mask); in hlwd_pic_mask_and_ack()
49 out_be32(io_base + HW_BROADWAY_ICR, mask); in hlwd_pic_mask_and_ack()
110 void __iomem *io_base = h->host_data; in __hlwd_pic_get_irq() local
114 in_be32(io_base + HW_BROADWAY_IMR); in __hlwd_pic_get_irq()
152 out_be32(io_base + HW_BROADWAY_IMR, 0); in __hlwd_quiesce()
160 void __iomem *io_base; in hlwd_pic_init() local
169 if (!io_base) { in hlwd_pic_init()
176 __hlwd_quiesce(io_base); in hlwd_pic_init()
179 &hlwd_irq_domain_ops, io_base); in hlwd_pic_init()
182 iounmap(io_base); in hlwd_pic_init()
[all …]
/linux/sound/isa/
A Dsscape.c133 unsigned io_base; member
191 outb(reg, ODIE_ADDR_IO(io_base)); in sscape_write_unsafe()
192 outb(val, ODIE_DATA_IO(io_base)); in sscape_write_unsafe()
216 outb(reg, ODIE_ADDR_IO(io_base)); in sscape_read_unsafe()
225 outb(0x0, HOST_CTRL_IO(io_base)); in set_host_mode_unsafe()
233 outb(0x3, HOST_CTRL_IO(io_base)); in set_midi_mode_unsafe()
336 sscape_write_unsafe(io_base, reg, in sscape_start_dma_unsafe()
338 sscape_write_unsafe(io_base, reg, in sscape_start_dma_unsafe()
474 outb(0x0, s->io_base); in upload_dma_data()
962 sscape->io_base = port[dev]; in create_sscape()
[all …]
/linux/drivers/crypto/hisilicon/sec2/
A Dsec_main.c349 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_open_sva_prefetch()
368 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_close_sva_prefetch()
392 val = readl(qm->io_base + SEC_CORE_AUTO_GATE); in sec_enable_clock_gate()
394 writel(val, qm->io_base + SEC_CORE_AUTO_GATE); in sec_enable_clock_gate()
448 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); in sec_engine_init()
496 readl(qm->io_base + sec_dfx_regs[i].offset); in sec_debug_regs_clear()
508 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
520 writel(val1, qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
717 regset->base = qm->io_base; in sec_core_debug_init()
793 err_val = readl(qm->io_base + in sec_log_hw_error()
[all …]
/linux/drivers/crypto/hisilicon/hpre/
A Dhpre_main.c383 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); in disable_flr_of_bme()
386 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); in disable_flr_of_bme()
438 val = readl(qm->io_base + HPRE_CLKGATE_CTL); in hpre_enable_clock_gate()
440 writel(val, qm->io_base + HPRE_CLKGATE_CTL); in hpre_enable_clock_gate()
462 val = readl(qm->io_base + HPRE_CLKGATE_CTL); in hpre_disable_clock_gate()
464 writel(val, qm->io_base + HPRE_CLKGATE_CTL); in hpre_disable_clock_gate()
499 qm->io_base + HPRE_TYPES_ENB); in hpre_set_user_domain_and_cache()
504 writel(0x0, qm->io_base + HPRE_BD_ENDIAN); in hpre_set_user_domain_and_cache()
505 writel(0x0, qm->io_base + HPRE_INT_MASK); in hpre_set_user_domain_and_cache()
508 writel(0x0, qm->io_base + HPRE_ECC_BYPASS); in hpre_set_user_domain_and_cache()
[all …]
/linux/drivers/watchdog/
A Dni903x_wdt.c40 u16 io_base; member
58 u8 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_start()
85 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
87 outb(control, wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
89 counter2 = inb(wdt->io_base + NIWD_COUNTER2); in ni903x_wdd_get_timeleft()
103 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_wdd_ping()
114 wdt->io_base + NIWD_CONTROL); in ni903x_wdd_start()
138 if (wdt->io_base != 0) { in ni903x_resources()
143 wdt->io_base = res->data.io.minimum; in ni903x_resources()
219 wdt->io_base + NIWD_CONTROL); in ni903x_acpi_add()
[all …]
A Dnic7018_wdt.c46 u16 io_base; member
96 wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_set_timeout()
114 outb(1, wdt->io_base + WDT_RELOAD_PORT); in nic7018_start()
116 control = inb(wdt->io_base + WDT_CTRL); in nic7018_start()
126 outb(0, wdt->io_base + WDT_CTRL); in nic7018_stop()
127 outb(0, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_stop()
137 outb(1, wdt->io_base + WDT_RELOAD_PORT); in nic7018_ping()
194 wdt->io_base = io_rc->start; in nic7018_probe()
212 outb(LOCK, wdt->io_base + WDT_REG_LOCK); in nic7018_probe()
217 wdt->io_base, timeout, nowayout); in nic7018_probe()
[all …]
/linux/sound/soc/spear/
A Dspdif_in.c38 void *io_base; member
52 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_configure()
53 writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_configure()
91 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_format()
128 ctrl = readl(host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
130 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
196 writel(0, host->io_base + SPDIF_IN_IRQ); in spdif_in_irq()
206 void __iomem *io_base; in spdif_in_probe() local
210 if (IS_ERR(io_base)) in spdif_in_probe()
211 return PTR_ERR(io_base); in spdif_in_probe()
[all …]
A Dspdif_out.c39 void __iomem *io_base; member
49 host->io_base + SPDIF_OUT_SOFT_RST); in spdif_out_configure()
54 host->io_base + SPDIF_OUT_CFG); in spdif_out_configure()
99 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); in spdif_out_clock()
102 writel(ctrl, host->io_base + SPDIF_OUT_CTRL); in spdif_out_clock()
178 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); in spdif_out_trigger()
181 writel(ctrl, host->io_base + SPDIF_OUT_CTRL); in spdif_out_trigger()
197 val = readl(host->io_base + SPDIF_OUT_CTRL); in spdif_mute()
209 writel(val, host->io_base + SPDIF_OUT_CTRL); in spdif_mute()
291 if (IS_ERR(host->io_base)) in spdif_out_probe()
[all …]
/linux/drivers/crypto/keembay/
A Docs-hcu.c182 writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_ISR); in ocs_hcu_done_irq_en()
186 hcu_dev->io_base + OCS_HCU_IER); in ocs_hcu_done_irq_en()
196 hcu_dev->io_base + OCS_HCU_DMA_MSI_IER); in ocs_hcu_dma_irq_en()
270 chain[i] = readl(hcu_dev->io_base + OCS_HCU_CHAIN); in ocs_hcu_get_intermediate_data()
301 writel(chain[i], hcu_dev->io_base + OCS_HCU_CHAIN); in ocs_hcu_set_intermediate_data()
328 chain[i] = readl(hcu_dev->io_base + OCS_HCU_CHAIN); in ocs_hcu_get_digest()
365 writel(cfg, hcu_dev->io_base + OCS_HCU_MODE); in ocs_hcu_hw_cfg()
472 writel(0, hcu_dev->io_base + OCS_HCU_DMA_SRC_SIZE); in ocs_hcu_ll_dma_start()
473 writel(0, hcu_dev->io_base + OCS_HCU_DMA_DST_SIZE); in ocs_hcu_ll_dma_start()
815 hcu_irq = readl(hcu_dev->io_base + OCS_HCU_ISR); in ocs_hcu_irq_handler()
[all …]
/linux/drivers/fpga/
A Dts73xx-fpga.c31 void __iomem *io_base; member
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
65 writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG); in ts73xx_fpga_write()
79 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
81 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
84 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
86 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
88 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
115 priv->io_base = devm_ioremap_resource(kdev, res); in ts73xx_fpga_probe()
116 if (IS_ERR(priv->io_base)) in ts73xx_fpga_probe()
[all …]
/linux/drivers/hwspinlock/
A Du8500_hsem.c90 void __iomem *io_base; in u8500_hsem_probe() local
97 io_base = devm_platform_ioremap_resource(pdev, 0); in u8500_hsem_probe()
98 if (IS_ERR(io_base)) in u8500_hsem_probe()
99 return PTR_ERR(io_base); in u8500_hsem_probe()
102 val = readl(io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
103 writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
106 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_probe()
116 hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i; in u8500_hsem_probe()
126 void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET; in u8500_hsem_remove() local
129 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_remove()
/linux/drivers/mtd/spi-nor/controllers/
A Dnxp-spifi.c57 void __iomem *io_base; member
141 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_read_reg()
165 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_write_reg()
200 writel(to, spifi->io_base + SPIFI_ADDR); in nxp_spifi_write()
207 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_write()
229 writel(offs, spifi->io_base + SPIFI_ADDR); in nxp_spifi_erase()
234 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_erase()
391 if (IS_ERR(spifi->io_base)) in nxp_spifi_probe()
392 return PTR_ERR(spifi->io_base); in nxp_spifi_probe()
427 writel(0, spifi->io_base + SPIFI_IDATA); in nxp_spifi_probe()
[all …]
/linux/drivers/mtd/nand/raw/
A Dlpc32xx_slc.c220 void __iomem *io_base; member
246 writel(0, SLC_CFG(host->io_base)); in lpc32xx_nand_setup()
247 writel(0, SLC_IEN(host->io_base)); in lpc32xx_nand_setup()
249 SLC_ICR(host->io_base)); in lpc32xx_nand_setup()
265 writel(tmp, SLC_TAC(host->io_base)); in lpc32xx_nand_setup()
517 SLC_CFG(host->io_base)); in lpc32xx_xfer()
528 SLC_CTRL(host->io_base)); in lpc32xx_xfer()
572 readl(SLC_ECC(host->io_base)); in lpc32xx_xfer()
586 SLC_CTRL(host->io_base)); in lpc32xx_xfer()
844 if (IS_ERR(host->io_base)) in lpc32xx_nand_probe()
[all …]
A Dlpc32xx_mlc.c180 void __iomem *io_base; member
250 writel(tmp, MLC_ICR(host->io_base)); in lpc32xx_nand_setup()
269 MLC_IRQ_MR(host->io_base)); in lpc32xx_nand_setup()
285 writel(cmd, MLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
298 if ((readb(MLC_ISR(host->io_base)) & in lpc32xx_nand_device_ready()
482 readl(MLC_BUFF(host->io_base)); in lpc32xx_read_page()
488 readl(MLC_BUFF(host->io_base)); in lpc32xx_read_page()
530 MLC_BUFF(host->io_base)); in lpc32xx_write_page_lowlevel()
702 if (IS_ERR(host->io_base)) in lpc32xx_nand_probe()
703 return PTR_ERR(host->io_base); in lpc32xx_nand_probe()
[all …]
/linux/drivers/mtd/devices/
A Dspear_smi.c174 void __iomem *io_base; member
235 dev->io_base + SMI_CR2); in spear_smi_read_sr()
249 writel(0, dev->io_base + SMI_CR2); in spear_smi_read_sr()
307 writel(0, dev->io_base + SMI_SR); in spear_smi_int_handler()
343 writel(0, dev->io_base + SMI_SR); in spear_smi_hw_init()
345 writel(val, dev->io_base + SMI_CR1); in spear_smi_hw_init()
399 writel(0, dev->io_base + SMI_CR2); in spear_smi_write_enable()
467 dev->io_base + SMI_CR2); in spear_smi_erase_sector()
480 writel(0, dev->io_base + SMI_CR2); in spear_smi_erase_sector()
981 if (IS_ERR(dev->io_base)) { in spear_smi_probe()
[all …]
/linux/drivers/spi/
A Dspi-stm32-qspi.c104 void __iomem *io_base; member
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
149 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
192 tx_fifo(buf++, qspi->io_base + QSPI_DR); in stm32_qspi_tx_poll()
247 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
315 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_wait_cmd()
387 qspi->io_base + QSPI_DLR); in stm32_qspi_send()
700 if (IS_ERR(qspi->io_base)) { in stm32_qspi_probe()
[all …]
/linux/drivers/input/keyboard/
A Dspear-keyboard.c57 void __iomem *io_base; member
76 sts = readl_relaxed(kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
86 val = readl_relaxed(kbd->io_base + DATA_REG) & in spear_kbd_interrupt()
97 writel_relaxed(0, kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
121 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
122 writel_relaxed(1, kbd->io_base + STATUS_REG); in spear_kbd_open()
125 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
127 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
224 if (IS_ERR(kbd->io_base)) in spear_kbd_probe()
225 return PTR_ERR(kbd->io_base); in spear_kbd_probe()
[all …]
/linux/drivers/crypto/hisilicon/zip/
A Dzip_main.c296 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
315 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
331 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); in hisi_zip_enable_clock_gate()
333 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); in hisi_zip_enable_clock_gate()
342 void __iomem *base = qm->io_base; in hisi_zip_set_user_domain_and_cache()
415 qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
425 qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); in hisi_zip_hw_error_enable()
611 regset->base = qm->io_base + core_offsets[i]; in hisi_zip_core_debug_init()
695 readl(qm->io_base + core_offsets[i] + in hisi_zip_debug_regs_clear()
726 err_val = readl(qm->io_base + in hisi_zip_log_hw_error()
[all …]

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