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Searched refs:io_p2v (Results 1 – 20 of 20) sorted by relevance

/linux/arch/arm/mach-pxa/include/mach/
A Dregs-ost.h11 #define OSMR0 io_p2v(0x40A00000) /* */
12 #define OSMR1 io_p2v(0x40A00004) /* */
13 #define OSMR2 io_p2v(0x40A00008) /* */
14 #define OSMR3 io_p2v(0x40A0000C) /* */
15 #define OSMR4 io_p2v(0x40A00080) /* */
16 #define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */
17 #define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */
18 #define OMCR4 io_p2v(0x40A000C0) /* */
19 #define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */
20 #define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */
[all …]
A Dpxa2xx-regs.h134 #define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */
135 #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */
136 #define CKEN io_p2v(0x41300004) /* Clock Enable Register */
137 #define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */
A Dmtd-xip.h19 #define ICIP io_p2v(0x40d00000)
20 #define ICMR io_p2v(0x40d00004)
A Dhardware.h37 #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) macro
40 # define __REG(x) (*((volatile u32 __iomem *)io_p2v(x)))
51 # define __REG(x) io_p2v(x)
A Ddma.h15 #define DMAC_REGS_VIRT io_p2v(0x40000000)
A Dpxa3xx-regs.h18 #define OSCC io_p2v(0x41350000) /* Oscillator Configuration Register */
/linux/arch/arm/mach-lpc32xx/
A Dlpc32xx.h121 #define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\
576 #define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00)
578 #define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08)
581 #define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14)
586 #define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00)
588 #define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08)
589 #define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
590 #define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10)
629 #define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C)
631 #define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14)
[all …]
A Dcommon.c41 iramptr1 = io_p2v(LPC32XX_IRAM_BASE); in lpc32xx_return_iram()
42 iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE); in lpc32xx_return_iram()
59 *mapbase = io_p2v(LPC32XX_IRAM_BASE); in lpc32xx_return_iram()
A Dpm.c124 #define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
/linux/arch/arm/mach-sa1100/include/mach/
A Dhardware.h35 #define io_p2v( x ) \ macro
40 #define __MREG(x) IOMEM(io_p2v(x))
44 # define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x)))
49 # define __REG(x) io_p2v(x)
A DSA-1100.h834 #define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */
835 #define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */
836 #define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */
837 #define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */
838 #define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */
839 #define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */
840 #define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
841 #define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */
/linux/arch/arm/mach-pxa/
A Dirq.c172 pxa_irq_base = io_p2v(0x40d00000); in pxa_init_irq()
257 pxa_irq_base = io_p2v(res.start); in pxa_dt_irq_init()
A Dgeneric.c54 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000)); in pxa_timer_init()
A Dpxa300.c86 mfp_init_base(io_p2v(MFPR_BASE)); in pxa300_init()
A Dpxa320.c80 mfp_init_base(io_p2v(MFPR_BASE)); in pxa320_init()
A Dpxa27x-udc.h178 #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
A Dpxa930.c202 mfp_init_base(io_p2v(MFPR_BASE)); in pxa930_init()
/linux/arch/arm/mach-ux500/
A Ddb8500-regs.h191 #define io_p2v(n) __io_address(n) macro
/linux/arch/arm/mach-sa1100/
A Dgeneric.c411 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000)); in sa1100_timer_init()
A Dassabet.c637 unsigned long virt = (unsigned long)io_p2v(phys); in map_sa1100_gpio_regs()

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