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Searched refs:irq_mask (Results 1 – 25 of 646) sorted by relevance

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/linux/arch/arm/mach-pxa/
A Dpxa_cplds_irqs.c29 unsigned int irq_mask; member
41 pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask; in cplds_irq_handler()
55 fpga->irq_mask &= ~bit; in cplds_irq_mask()
56 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); in cplds_irq_mask()
68 fpga->irq_mask |= bit; in cplds_irq_unmask()
69 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); in cplds_irq_unmask()
75 .irq_mask = cplds_irq_mask,
100 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); in cplds_resume()
137 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); in cplds_probe()
/linux/arch/mips/sgi-ip27/
A Dip27-irq.c27 u64 *irq_mask[2]; member
56 __raw_writeq(mask[0], hd->irq_mask[0]); in enable_hub_irq()
57 __raw_writeq(mask[1], hd->irq_mask[1]); in enable_hub_irq()
66 __raw_writeq(mask[0], hd->irq_mask[0]); in disable_hub_irq()
67 __raw_writeq(mask[1], hd->irq_mask[1]); in disable_hub_irq()
82 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_A); in setup_hub_mask()
83 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_A); in setup_hub_mask()
85 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B); in setup_hub_mask()
86 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B); in setup_hub_mask()
113 .irq_mask = disable_hub_irq,
/linux/drivers/gpio/
A Dgpio-104-idi-48.c49 unsigned char irq_mask[6]; member
126 idi48gpio->irq_mask[boundary] &= ~mask; in idi_48_irq_mask()
128 if (!idi48gpio->irq_mask[boundary]) { in idi_48_irq_mask()
157 prev_irq_mask = idi48gpio->irq_mask[boundary]; in idi_48_irq_unmask()
159 idi48gpio->irq_mask[boundary] |= mask; in idi_48_irq_unmask()
188 .irq_mask = idi_48_irq_mask,
198 unsigned long irq_mask; in idi_48_irq_handler() local
221 irq_mask = idi48gpio->irq_mask[boundary]; in idi_48_irq_handler()
223 for_each_set_bit(bit_num, &irq_mask, 8) { in idi_48_irq_handler()
A Dgpio-104-dio-48e.c53 unsigned char irq_mask; member
271 dio48egpio->irq_mask &= ~BIT(0); in dio48e_irq_mask()
273 dio48egpio->irq_mask &= ~BIT(1); in dio48e_irq_mask()
275 if (!dio48egpio->irq_mask) in dio48e_irq_mask()
295 if (!dio48egpio->irq_mask) { in dio48e_irq_unmask()
302 dio48egpio->irq_mask |= BIT(0); in dio48e_irq_unmask()
304 dio48egpio->irq_mask |= BIT(1); in dio48e_irq_unmask()
326 .irq_mask = dio48e_irq_mask,
335 const unsigned long irq_mask = dio48egpio->irq_mask; in dio48e_irq_handler() local
338 for_each_set_bit(gpio, &irq_mask, 2) in dio48e_irq_handler()
A Dgpio-104-idio-16.c46 unsigned long irq_mask; member
156 idio16gpio->irq_mask &= ~mask; in idio_16_irq_mask()
158 if (!idio16gpio->irq_mask) { in idio_16_irq_mask()
172 const unsigned long prev_irq_mask = idio16gpio->irq_mask; in idio_16_irq_unmask()
175 idio16gpio->irq_mask |= mask; in idio_16_irq_unmask()
199 .irq_mask = idio_16_irq_mask,
210 for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio) in idio_16_irq_handler()
A Dgpio-pcie-idio-24.c138 unsigned long irq_mask; member
384 idio24gpio->irq_mask &= ~BIT(bit_offset); in idio_24_irq_mask()
385 new_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; in idio_24_irq_mask()
413 prev_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; in idio_24_irq_unmask()
414 idio24gpio->irq_mask |= BIT(bit_offset); in idio_24_irq_unmask()
443 .irq_mask = idio_24_irq_mask,
453 unsigned long irq_mask; in idio_24_irq_handler() local
468 irq_mask = idio24gpio->irq_mask & irq_status; in idio_24_irq_handler()
470 for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24) in idio_24_irq_handler()
A Dgpio-pci-idio-16.c57 unsigned long irq_mask; member
197 idio16gpio->irq_mask &= ~mask; in idio_16_irq_mask()
199 if (!idio16gpio->irq_mask) { in idio_16_irq_mask()
213 const unsigned long prev_irq_mask = idio16gpio->irq_mask; in idio_16_irq_unmask()
216 idio16gpio->irq_mask |= mask; in idio_16_irq_unmask()
240 .irq_mask = idio_16_irq_mask,
262 for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio) in idio_16_irq_handler()
A Dgpio-ws16c48.c48 unsigned long irq_mask; member
220 port_state = ws16c48gpio->irq_mask >> (8*port); in ws16c48_irq_ack()
245 ws16c48gpio->irq_mask &= ~mask; in ws16c48_irq_mask()
248 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); in ws16c48_irq_mask()
269 ws16c48gpio->irq_mask |= mask; in ws16c48_irq_unmask()
272 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); in ws16c48_irq_unmask()
319 .irq_mask = ws16c48_irq_mask,
/linux/drivers/thermal/intel/
A Dintel_bxt_pmic_thermal.c33 u8 irq_mask; member
53 .irq_mask = 0x01,
62 .irq_mask = 0x10,
74 .irq_mask = 0x02,
83 .irq_mask = 0x20,
95 .irq_mask = 0x04,
104 .irq_mask = 0x40,
116 .irq_mask = 0x10,
173 mask = td->maps[i].trip_config[j].irq_mask; in pmic_thermal_irq_handler()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
A Ddispc-compat.c514 u32 irq_mask; in dispc_mgr_enable_digit_out() local
529 irq_mask); in dispc_mgr_enable_digit_out()
531 DSSERR("failed to register %x isr\n", irq_mask); in dispc_mgr_enable_digit_out()
542 irq_mask); in dispc_mgr_enable_digit_out()
544 DSSERR("failed to unregister %x isr\n", irq_mask); in dispc_mgr_enable_digit_out()
551 u32 irq_mask; in dispc_mgr_disable_digit_out() local
565 if (!irq_mask) { in dispc_mgr_disable_digit_out()
582 irq_mask); in dispc_mgr_disable_digit_out()
584 DSSERR("failed to register %x isr\n", irq_mask); in dispc_mgr_disable_digit_out()
601 irq_mask); in dispc_mgr_disable_digit_out()
[all …]
/linux/arch/arm/mach-omap2/
A Ddisplay.c279 u32 v, irq_mask = 0; in dispc_disable_outputs() local
323 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT; in dispc_disable_outputs()
327 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT; in dispc_disable_outputs()
329 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT | in dispc_disable_outputs()
335 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT; in dispc_disable_outputs()
337 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT; in dispc_disable_outputs()
343 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS); in dispc_disable_outputs()
365 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) != in dispc_disable_outputs()
366 irq_mask) { in dispc_disable_outputs()
/linux/arch/alpha/kernel/
A Dsys_rx164.c40 volatile unsigned int *irq_mask; in rx164_update_irq_hw() local
42 irq_mask = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x74); in rx164_update_irq_hw()
43 *irq_mask = mask; in rx164_update_irq_hw()
45 *irq_mask; in rx164_update_irq_hw()
63 .irq_mask = rx164_disable_irq,
/linux/drivers/i2c/busses/
A Di2c-cht-wc.c49 u8 irq_mask; member
71 reg &= ~adap->irq_mask; in cht_wc_i2c_adap_thread_handler()
239 if (adap->irq_mask != adap->old_irq_mask) { in cht_wc_i2c_irq_sync_unlock()
241 adap->irq_mask); in cht_wc_i2c_irq_sync_unlock()
243 adap->old_irq_mask = adap->irq_mask; in cht_wc_i2c_irq_sync_unlock()
255 adap->irq_mask &= ~CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; in cht_wc_i2c_irq_enable()
262 adap->irq_mask |= CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; in cht_wc_i2c_irq_disable()
342 adap->old_irq_mask = adap->irq_mask = ~CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK; in cht_wc_i2c_adap_i2c_probe()
348 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, ~adap->irq_mask); in cht_wc_i2c_adap_i2c_probe()
352 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, adap->irq_mask); in cht_wc_i2c_adap_i2c_probe()
A Di2c-nomadik.c447 u32 mcr, irq_mask; in read_i2c() local
463 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | in read_i2c()
467 irq_mask |= I2C_IT_MTD; in read_i2c()
469 irq_mask |= I2C_IT_MTDWS; in read_i2c()
471 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); in read_i2c()
473 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, in read_i2c()
516 u32 mcr, irq_mask; in write_i2c() local
539 irq_mask |= I2C_IT_TXFNE; in write_i2c()
547 irq_mask |= I2C_IT_MTD; in write_i2c()
549 irq_mask |= I2C_IT_MTDWS; in write_i2c()
[all …]
/linux/drivers/gpu/drm/omapdrm/
A Domap_irq.c23 u32 irqmask = priv->irq_mask; in omap_irq_update()
92 priv->irq_mask |= framedone_irq; in omap_irq_enable_framedone()
94 priv->irq_mask &= ~framedone_irq; in omap_irq_enable_framedone()
123 priv->irq_mask |= dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_enable_vblank()
149 priv->irq_mask &= ~dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_disable_vblank()
177 irqstatus &= priv->irq_mask & mask; in omap_irq_fifo_underflow()
267 priv->irq_mask = DISPC_IRQ_OCP_ERR; in omap_drm_irq_install()
273 priv->irq_mask |= omap_underflow_irqs[i]; in omap_drm_irq_install()
277 priv->irq_mask |= dispc_mgr_get_sync_lost_irq(priv->dispc, i); in omap_drm_irq_install()
/linux/drivers/gpu/drm/i915/gt/
A Dgen2_engine_cs.c295 i915->irq_mask &= ~engine->irq_enable_mask; in gen2_irq_enable()
296 intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); in gen2_irq_enable()
304 i915->irq_mask |= engine->irq_enable_mask; in gen2_irq_disable()
305 intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); in gen2_irq_disable()
310 engine->i915->irq_mask &= ~engine->irq_enable_mask; in gen3_irq_enable()
311 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); in gen3_irq_enable()
317 engine->i915->irq_mask |= engine->irq_enable_mask; in gen3_irq_disable()
318 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); in gen3_irq_disable()
/linux/drivers/gpu/drm/tidss/
A Dtidss_irq.c23 dispc_set_irqenable(tidss->dispc, tidss->irq_mask); in tidss_irq_update()
35 tidss->irq_mask |= DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) | in tidss_irq_enable_vblank()
50 tidss->irq_mask &= ~(DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) | in tidss_irq_disable_vblank()
120 tidss->irq_mask = DSS_IRQ_DEVICE_OCP_ERR; in tidss_irq_postinstall()
125 tidss->irq_mask |= DSS_IRQ_VP_SYNC_LOST(tcrtc->hw_videoport); in tidss_irq_postinstall()
127 tidss->irq_mask |= DSS_IRQ_VP_FRAME_DONE(tcrtc->hw_videoport); in tidss_irq_postinstall()
/linux/arch/arm/mach-cns3xxx/
A Dcore.c198 u32 irq_mask; in __cns3xxx_timer_init() local
217 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
218 irq_mask &= ~(1 << 2); in __cns3xxx_timer_init()
219 irq_mask |= 0x03; in __cns3xxx_timer_init()
220 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
232 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
233 irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); in __cns3xxx_timer_init()
234 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
/linux/drivers/irqchip/
A Dexynos-combiner.c31 unsigned int irq_mask; member
78 status &= chip_data->irq_mask; in combiner_handle_cascade_irq()
109 .irq_mask = combiner_mask_irq,
129 combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3); in combiner_init_one()
133 writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR); in combiner_init_one()
231 writel_relaxed(combiner_data[i].irq_mask, in combiner_resume()
/linux/arch/mips/sgi-ip32/
A Dip32-irq.c140 .irq_mask = crime_disable_irq,
160 .irq_mask = crime_disable_irq,
193 .irq_mask = disable_macepci_irq,
292 .irq_mask = disable_maceisa_irq,
299 .irq_mask = disable_maceisa_irq,
327 .irq_mask = disable_mace_irq,
/linux/drivers/gpu/drm/arm/
A Dhdlcd_drv.c83 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); in hdlcd_irq_postinstall() local
86 irq_mask |= HDLCD_DEBUG_INT_MASK; in hdlcd_irq_postinstall()
88 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask); in hdlcd_irq_postinstall()
114 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); in hdlcd_irq_uninstall() local
118 irq_mask &= ~HDLCD_DEBUG_INT_MASK; in hdlcd_irq_uninstall()
122 irq_mask &= ~HDLCD_INTERRUPT_VSYNC; in hdlcd_irq_uninstall()
123 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask); in hdlcd_irq_uninstall()
A Dmalidp_hw.c947 .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
957 .irq_mask = MALIDP500_SE_IRQ_CONF_MODE |
966 .irq_mask = MALIDP500_DE_IRQ_CONF_VALID,
999 .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
1007 .irq_mask = MALIDP550_SE_IRQ_EOW,
1047 .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
1061 .irq_mask = MALIDP550_SE_IRQ_EOW,
1206 if (!(status & de->irq_mask)) in malidp_de_irq()
1246 hwdev->hw->map.dc_irq_map.irq_mask); in malidp_de_irq_hw_init()
1250 hwdev->hw->map.de_irq_map.irq_mask); in malidp_de_irq_hw_init()
[all …]
/linux/arch/mips/loongson2ef/lemote-2f/
A Dpm.c54 int irq_mask; in setup_wakeup_events() local
61 irq_mask = inb(PIC_MASTER_IMR); in setup_wakeup_events()
67 outb(irq_mask & ~(1 << PIC_CASCADE_IR), PIC_MASTER_IMR); in setup_wakeup_events()
/linux/drivers/gpu/drm/vmwgfx/
A Dvmwgfx_irq.c87 masked_status = status & READ_ONCE(dev_priv->irq_mask); in vmw_irq_handler()
238 dev_priv->irq_mask |= flag; in vmw_generic_waiter_add()
239 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
249 dev_priv->irq_mask &= ~flag; in vmw_generic_waiter_remove()
250 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_remove()
/linux/drivers/mfd/
A Ducb1x00-core.c303 ucb->irq_mask); in ucb1x00_irq_update()
306 ucb->irq_mask); in ucb1x00_irq_update()
320 ucb->irq_mask &= ~mask; in ucb1x00_irq_mask()
331 ucb->irq_mask |= mask; in ucb1x00_irq_unmask()
351 if (ucb->irq_mask & mask) { in ucb1x00_irq_set_type()
353 ucb->irq_mask); in ucb1x00_irq_set_type()
355 ucb->irq_mask); in ucb1x00_irq_set_type()
384 .irq_mask = ucb1x00_irq_mask,
714 ucb->irq_mask); in ucb1x00_resume()
716 ucb->irq_mask); in ucb1x00_resume()

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