Searched refs:khz_to_mhz_ceil (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr_vbios_smu.c | 129 khz_to_mhz_ceil(requested_dispclk_khz)); in rn_vbios_smu_set_dispclk()
141 ASSERT(actual_dispclk_set_mhz >= khz_to_mhz_ceil(requested_dispclk_khz)); in rn_vbios_smu_set_dispclk()
153 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in rn_vbios_smu_set_dprefclk()
170 khz_to_mhz_ceil(requested_dcfclk_khz)); in rn_vbios_smu_set_hard_min_dcfclk()
185 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); in rn_vbios_smu_set_min_deep_sleep_dcfclk()
195 khz_to_mhz_ceil(requested_phyclk_khz)); in rn_vbios_smu_set_phyclk()
206 khz_to_mhz_ceil(requested_dpp_khz)); in rn_vbios_smu_set_dppclk()
209 ASSERT(actual_dppclk_set_mhz >= khz_to_mhz_ceil(requested_dpp_khz)); in rn_vbios_smu_set_dppclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | dcn301_smu.c | 136 khz_to_mhz_ceil(requested_dispclk_khz)); in dcn301_smu_set_dispclk()
150 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn301_smu_set_dprefclk()
166 khz_to_mhz_ceil(requested_dcfclk_khz)); in dcn301_smu_set_hard_min_dcfclk()
180 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); in dcn301_smu_set_min_deep_sleep_dcfclk()
194 khz_to_mhz_ceil(requested_dpp_khz)); in dcn301_smu_set_dppclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_smu.c | 150 khz_to_mhz_ceil(requested_dispclk_khz)); in dcn31_smu_set_dispclk()
165 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn31_smu_set_dprefclk()
185 khz_to_mhz_ceil(requested_dcfclk_khz)); in dcn31_smu_set_hard_min_dcfclk()
203 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); in dcn31_smu_set_min_deep_sleep_dcfclk()
218 khz_to_mhz_ceil(requested_dpp_khz)); in dcn31_smu_set_dppclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| A D | rv1_clk_mgr.c | 267 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
268 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
269 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_k… in rv1_update_clocks()
287 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
288 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
289 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_k… in rv1_update_clocks()
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| A D | rv1_clk_mgr_vbios_smu.c | 133 khz_to_mhz_ceil(requested_dispclk_khz)); in rv1_vbios_smu_set_dispclk()
153 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in rv1_vbios_smu_set_dprefclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| A D | dcn30_clk_mgr.c | 287 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_k… in dcn3_update_clocks()
292 …dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_slee… in dcn3_update_clocks()
320 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz… in dcn3_update_clocks()
327 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_kh… in dcn3_update_clocks()
333 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_… in dcn3_update_clocks()
402 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); in dcn3_set_hard_min_memclk()
497 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_kh… in dcn30_notify_link_rate_change()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.c | 266 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
273 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_… in dcn2_update_clocks()
279 …pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.socclk_khz… in dcn2_update_clocks()
294 …pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)… in dcn2_update_clocks()
319 …pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks… in dcn2_update_clocks()
515 …pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.… in dcn2_notify_link_rate_change()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | clk_mgr_internal.h | 334 static inline int khz_to_mhz_ceil(int khz) in khz_to_mhz_ceil() function
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