/linux/drivers/gpu/drm/bridge/analogix/ |
A D | analogix_dp_core.c | 263 lane_count = dp->link_train.lane_count; in analogix_dp_link_start() 320 lane_count); in analogix_dp_link_start() 349 int lane_count) in analogix_dp_channel_eq_ok() argument 445 int lane, lane_count; in analogix_dp_get_adjust_training_lane() local 448 lane_count = dp->link_train.lane_count; in analogix_dp_get_adjust_training_lane() 468 int lane, lane_count, retval; in analogix_dp_process_clock_recovery() local 474 lane_count = dp->link_train.lane_count; in analogix_dp_process_clock_recovery() 540 int lane, lane_count, retval; in analogix_dp_process_equalizer_training() local 546 lane_count = dp->link_train.lane_count; in analogix_dp_process_equalizer_training() 584 dp->link_train.lane_count); in analogix_dp_process_equalizer_training() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/core/ |
A D | dc_link_dpia.c | 266 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_non_transparent() local 361 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_non_transparent() 366 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_non_transparent() 422 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_transparent() local 464 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_transparent() 574 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_non_transparent() local 660 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_non_transparent() 665 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in dpia_training_eq_non_transparent() 711 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_transparent() local 743 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_transparent() [all …]
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A D | dc_link_dp.c | 1170 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_channel_equalization_sequence() local 1267 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_clock_recovery_sequence() local 1477 lt_settings->link_settings.lane_count = link_setting->lane_count; 2601 if (link->reported_link_cap.lane_count < max_link_cap.lane_count) 3004 switch (lane_count) { 3042 switch (lane_count) { 3084 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && 3094 if (dp_lt_fallbacks[next_idx].lane_count <= max->lane_count && 3101 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count; 3491 link->verified_link_cap.lane_count = link_settings.lane_count; [all …]
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/linux/drivers/gpu/drm/i915/display/ |
A D | intel_dp_link_training.c | 317 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset() 417 crtc_state->lane_count, in intel_dp_get_adjust_train() 425 crtc_state->lane_count, in intel_dp_get_adjust_train() 460 len = crtc_state->lane_count + 1; in intel_dp_set_link_train() 539 crtc_state->lane_count, in intel_dp_set_signal_levels() 547 crtc_state->lane_count, in intel_dp_set_signal_levels() 582 return ret == crtc_state->lane_count; in intel_dp_update_link_train() 668 link_config[1] = crtc_state->lane_count; in intel_dp_prepare_link_train() 959 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization() 969 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization() [all …]
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A D | intel_dpio_phy.c | 591 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask() 599 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask() 679 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level() 692 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level() 745 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level() 771 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset() 788 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset() 854 if (crtc_state->lane_count > 2) { in chv_phy_pre_pll_enable() 898 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable() 907 if (crtc_state->lane_count == 1) in chv_phy_pre_encoder_enable() [all …]
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A D | intel_dp.h | 43 int link_rate, int lane_count); 45 int link_rate, u8 lane_count); 100 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument 102 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
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A D | vlv_dsi.c | 51 8 * 100), lane_count); in txbyteclkhs() 58 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs() 1103 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local 1155 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config() 1209 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config() 1211 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config() 1213 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config() 1301 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings() local 1324 hactive = txbyteclkhs(hactive, bpp, lane_count, in set_dsi_timings() 1327 hsync = txbyteclkhs(hsync, bpp, lane_count, in set_dsi_timings() [all …]
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A D | intel_combo_phy.c | 258 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument 266 switch (lane_count) { in intel_combo_phy_power_up_lanes() 277 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes() 284 switch (lane_count) { in intel_combo_phy_power_up_lanes() 294 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
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A D | vlv_dsi_pll.c | 45 int lane_count) in dsi_clk_from_pclk() argument 52 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk() 126 intel_dsi->lane_count); in vlv_dsi_pll_compute() 317 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_get_pclk() 338 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_get_pclk() 468 intel_dsi->lane_count); in bxt_dsi_pll_compute()
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A D | intel_dp.c | 496 u8 lane_count) in intel_dp_link_params_valid() argument 507 if (lane_count == 0 || in intel_dp_link_params_valid() 516 u8 lane_count) in intel_dp_can_link_train_fallback_for_edp() argument 559 lane_count)) { in intel_dp_get_link_train_fallback_values() 566 } else if (lane_count > 1) { in intel_dp_get_link_train_fallback_values() 1198 int bpp, i, lane_count; in intel_dp_compute_link_config_wide() local 1215 lane_count <<= 1) { in intel_dp_compute_link_config_wide() 1217 lane_count); in intel_dp_compute_link_config_wide() 1220 pipe_config->lane_count = lane_count; in intel_dp_compute_link_config_wide() 1865 intel_dp->lane_count = lane_count; in intel_dp_set_link_params() [all …]
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A D | intel_combo_phy.h | 18 int lane_count, bool lane_reversal);
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A D | intel_dpio_phy.h | 28 u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
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A D | intel_ddi.c | 288 DDI_PORT_WIDTH(crtc_state->lane_count) | in intel_ddi_init_dp_buf_reg() 1032 if (crtc_state->lane_count == 4) in icl_combo_phy_loadgen_select() 2041 width = crtc_state->lane_count; in icl_program_mg_dp_mode() 2208 crtc_state->lane_count, in intel_ddi_power_up_lanes() 2295 crtc_state->lane_count); in dg2_ddi_pre_enable_dp() 2403 crtc_state->lane_count); in tgl_ddi_pre_enable_dp() 2545 crtc_state->lane_count); in hsw_ddi_pre_enable_dp() 3489 pipe_config->lane_count = 4; in intel_ddi_read_func_ctl() 3496 pipe_config->lane_count = in intel_ddi_read_func_ctl() 3528 pipe_config->lane_count = in intel_ddi_read_func_ctl() [all …]
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/linux/drivers/gpu/drm/msm/dp/ |
A D | dp_panel.h | 91 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument 93 return (lane_count == 1 || in is_lane_count_valid() 94 lane_count == 2 || in is_lane_count_valid() 95 lane_count == 4); in is_lane_count_valid()
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A D | dp_audio.h | 21 u32 lane_count; member
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/linux/drivers/gpu/drm/gma500/ |
A D | cdv_intel_dp.c | 266 uint8_t lane_count; member 902 int lane_count, clock; in cdv_intel_dp_mode_fixup() local 915 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup() 921 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup() 995 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local 1012 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n() 1015 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n() 1059 switch (intel_dp->lane_count) { in cdv_intel_dp_mode_set() 1392 intel_dp->lane_count); in cdv_intel_dplink_set_level() 1394 if (ret != intel_dp->lane_count) { in cdv_intel_dplink_set_level() [all …]
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/linux/drivers/gpu/drm/bridge/ |
A D | parade-ps8622.c | 55 u32 lane_count; member 185 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config() 500 &ps8622->lane_count)) { in ps8622_probe() 501 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe() 502 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe() 505 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
A D | amdgpu_dm_debugfs.c | 200 link->cur_link_settings.lane_count, in dp_link_settings_read() 207 link->verified_link_cap.lane_count, in dp_link_settings_read() 214 link->reported_link_cap.lane_count, in dp_link_settings_read() 221 link->preferred_link_setting.lane_count, in dp_link_settings_read() 315 prefer_link_settings.lane_count = param[0]; in dp_link_settings_write() 522 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write() 523 link->preferred_link_setting.lane_count; in dp_phy_settings_write() 530 link->cur_link_settings.lane_count; in dp_phy_settings_write() 717 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; in dp_phy_test_pattern_debugfs_write() 721 cur_link_settings.lane_count = link->cur_link_settings.lane_count; in dp_phy_test_pattern_debugfs_write() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
A D | dcn201_link_encoder.c | 64 if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO) in dcn201_link_encoder_get_max_link_cap() 65 link_settings->lane_count = LANE_COUNT_TWO; in dcn201_link_encoder_get_max_link_cap()
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/linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
A D | dcn31_dio_link_encoder.c | 424 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_output() 469 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_mst_output() 590 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
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A D | dcn31_hpo_dp_link_encoder.c | 455 NUM_LANES, &state->lane_count); in dcn31_hpo_dp_link_enc_read_state() 517 cntl.lanes_number = link_settings->lane_count; in dcn31_hpo_dp_link_enc_enable_dp_output() 572 cntl.lanes_number = link_settings->lane_count; in dcn31_hpo_dp_link_enc_set_ffe()
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/linux/drivers/gpu/drm/amd/display/dc/dce/ |
A D | dce_link_encoder.c | 608 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in configure_encoder() 622 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in dce60_configure_encoder() 1143 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_output() 1182 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_mst_output() 1222 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_output() 1261 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_mst_output() 1342 cntl.lanes_number = link_settings->link_settings.lane_count; in dce110_link_encoder_dp_set_lane_settings() 1347 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dce110_link_encoder_dp_set_lane_settings()
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/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
A D | dcn20_link_encoder.c | 221 for (i = 0; i < link_settings->lane_count; i++) in update_cfg_data() 281 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn20_link_encoder_get_max_link_cap()
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/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
A D | dcn10_link_encoder.c | 496 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in enc1_configure_encoder() 996 cntl.lanes_number = link_settings->lane_count; in dcn10_link_encoder_enable_dp_output() 1035 cntl.lanes_number = link_settings->lane_count; in dcn10_link_encoder_enable_dp_mst_output() 1118 cntl.lanes_number = link_settings->link_settings.lane_count; in dcn10_link_encoder_dp_set_lane_settings() 1123 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dcn10_link_encoder_dp_set_lane_settings()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
A D | dce110_clk_mgr.c | 155 cfg->link_settings.lane_count = in dce110_fill_display_configs() 156 stream->link->cur_link_settings.lane_count; in dce110_fill_display_configs()
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