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Searched refs:layers (Results 1 – 25 of 169) sorted by relevance

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/linux/security/landlock/
A Druleset.c71 const struct landlock_layer (*const layers)[], in create_rule() argument
96 memcpy(new_rule->layers, layers, in create_rule()
155 if (WARN_ON_ONCE(!object || !layers)) in insert_rule()
176 if ((*layers)[0].level == 0) { in insert_rule()
185 this->layers[0].access |= (*layers)[0].access; in insert_rule()
197 &(*layers)[0]); in insert_rule()
233 struct landlock_layer layers[] = {{ in landlock_insert_rule() local
240 return insert_rule(ruleset, object, &layers, ARRAY_SIZE(layers)); in landlock_insert_rule()
287 struct landlock_layer layers[] = {{ in merge_ruleset() local
299 layers[0].access = walker_rule->layers[0].access; in merge_ruleset()
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/linux/drivers/edac/
A Dpasemi_edac.c183 struct edac_mc_layer layers[2]; in pasemi_edac_probe() local
200 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in pasemi_edac_probe()
201 layers[0].size = PASEMI_EDAC_NR_CSROWS; in pasemi_edac_probe()
202 layers[0].is_virt_csrow = true; in pasemi_edac_probe()
203 layers[1].type = EDAC_MC_LAYER_CHANNEL; in pasemi_edac_probe()
204 layers[1].size = PASEMI_EDAC_NR_CHANS; in pasemi_edac_probe()
205 layers[1].is_virt_csrow = false; in pasemi_edac_probe()
206 mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers, in pasemi_edac_probe()
A Damd76x_edac.c237 struct edac_mc_layer layers[2]; in amd76x_probe1() local
246 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in amd76x_probe1()
247 layers[0].size = AMD76X_NR_CSROWS; in amd76x_probe1()
248 layers[0].is_virt_csrow = true; in amd76x_probe1()
249 layers[1].type = EDAC_MC_LAYER_CHANNEL; in amd76x_probe1()
250 layers[1].size = 1; in amd76x_probe1()
251 layers[1].is_virt_csrow = false; in amd76x_probe1()
252 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in amd76x_probe1()
A Dhighbank_mc_edac.c148 struct edac_mc_layer layers[2]; in highbank_mc_probe() local
162 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in highbank_mc_probe()
163 layers[0].size = 1; in highbank_mc_probe()
164 layers[0].is_virt_csrow = true; in highbank_mc_probe()
165 layers[1].type = EDAC_MC_LAYER_CHANNEL; in highbank_mc_probe()
166 layers[1].size = 1; in highbank_mc_probe()
167 layers[1].is_virt_csrow = false; in highbank_mc_probe()
168 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in highbank_mc_probe()
A Di82860_edac.c187 struct edac_mc_layer layers[2]; in i82860_probe1() local
200 layers[0].type = EDAC_MC_LAYER_CHANNEL; in i82860_probe1()
201 layers[0].size = 2; in i82860_probe1()
202 layers[0].is_virt_csrow = true; in i82860_probe1()
203 layers[1].type = EDAC_MC_LAYER_SLOT; in i82860_probe1()
204 layers[1].size = 8; in i82860_probe1()
205 layers[1].is_virt_csrow = true; in i82860_probe1()
206 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i82860_probe1()
A Dr82600_edac.c271 struct edac_mc_layer layers[2]; in r82600_probe1() local
285 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in r82600_probe1()
286 layers[0].size = R82600_NR_CSROWS; in r82600_probe1()
287 layers[0].is_virt_csrow = true; in r82600_probe1()
288 layers[1].type = EDAC_MC_LAYER_CHANNEL; in r82600_probe1()
289 layers[1].size = R82600_NR_CHANS; in r82600_probe1()
290 layers[1].is_virt_csrow = false; in r82600_probe1()
291 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in r82600_probe1()
A Dcell_edac.c172 struct edac_mc_layer layers[2]; in cell_edac_probe() local
202 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in cell_edac_probe()
203 layers[0].size = 1; in cell_edac_probe()
204 layers[0].is_virt_csrow = true; in cell_edac_probe()
205 layers[1].type = EDAC_MC_LAYER_CHANNEL; in cell_edac_probe()
206 layers[1].size = num_chans; in cell_edac_probe()
207 layers[1].is_virt_csrow = false; in cell_edac_probe()
208 mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, in cell_edac_probe()
A Daspeed_edac.c282 struct edac_mc_layer layers[2]; in aspeed_probe() local
307 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in aspeed_probe()
308 layers[0].size = 1; in aspeed_probe()
309 layers[0].is_virt_csrow = true; in aspeed_probe()
310 layers[1].type = EDAC_MC_LAYER_CHANNEL; in aspeed_probe()
311 layers[1].size = 1; in aspeed_probe()
312 layers[1].is_virt_csrow = false; in aspeed_probe()
314 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in aspeed_probe()
A Di82443bxgx_edac.c234 struct edac_mc_layer layers[2]; in i82443bxgx_edacmc_probe1() local
248 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82443bxgx_edacmc_probe1()
249 layers[0].size = I82443BXGX_NR_CSROWS; in i82443bxgx_edacmc_probe1()
250 layers[0].is_virt_csrow = true; in i82443bxgx_edacmc_probe1()
251 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82443bxgx_edacmc_probe1()
252 layers[1].size = I82443BXGX_NR_CHANS; in i82443bxgx_edacmc_probe1()
253 layers[1].is_virt_csrow = false; in i82443bxgx_edacmc_probe1()
254 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i82443bxgx_edacmc_probe1()
A Di3200_edac.c340 struct edac_mc_layer layers[2]; in i3200_probe1() local
355 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i3200_probe1()
356 layers[0].size = I3200_DIMMS; in i3200_probe1()
357 layers[0].is_virt_csrow = true; in i3200_probe1()
358 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i3200_probe1()
359 layers[1].size = nr_channels; in i3200_probe1()
360 layers[1].is_virt_csrow = false; in i3200_probe1()
361 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in i3200_probe1()
A Di3000_edac.c313 struct edac_mc_layer layers[2]; in i3000_probe1() local
356 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i3000_probe1()
357 layers[0].size = I3000_RANKS / nr_channels; in i3000_probe1()
358 layers[0].is_virt_csrow = true; in i3000_probe1()
359 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i3000_probe1()
360 layers[1].size = nr_channels; in i3000_probe1()
361 layers[1].is_virt_csrow = false; in i3000_probe1()
362 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i3000_probe1()
A Di82875p_edac.c391 struct edac_mc_layer layers[2]; in i82875p_probe1() local
406 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82875p_probe1()
407 layers[0].size = I82875P_NR_CSROWS(nr_chans); in i82875p_probe1()
408 layers[0].is_virt_csrow = true; in i82875p_probe1()
409 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82875p_probe1()
410 layers[1].size = nr_chans; in i82875p_probe1()
411 layers[1].is_virt_csrow = false; in i82875p_probe1()
412 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in i82875p_probe1()
A Dx38_edac.c322 struct edac_mc_layer layers[2]; in x38_probe1() local
338 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in x38_probe1()
339 layers[0].size = X38_RANKS; in x38_probe1()
340 layers[0].is_virt_csrow = true; in x38_probe1()
341 layers[1].type = EDAC_MC_LAYER_CHANNEL; in x38_probe1()
342 layers[1].size = x38_channel_num; in x38_probe1()
343 layers[1].is_virt_csrow = false; in x38_probe1()
344 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in x38_probe1()
A Docteon_edac-lmc.c228 struct edac_mc_layer layers[1]; in octeon_lmc_edac_probe() local
233 layers[0].type = EDAC_MC_LAYER_CHANNEL; in octeon_lmc_edac_probe()
234 layers[0].size = 1; in octeon_lmc_edac_probe()
235 layers[0].is_virt_csrow = false; in octeon_lmc_edac_probe()
246 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
278 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
A Dedac_mc.c70 edac_layer_name[mci->layers[i].type], in edac_dimm_info_location()
360 if (mci->layers[0].is_virt_csrow) { in edac_mc_alloc_dimms()
377 if (pos[layer] < mci->layers[layer].size) in edac_mc_alloc_dimms()
388 struct edac_mc_layer *layers, in edac_mc_alloc() argument
406 tot_dimms *= layers[idx].size; in edac_mc_alloc()
408 if (layers[idx].is_virt_csrow) in edac_mc_alloc()
409 tot_csrows *= layers[idx].size; in edac_mc_alloc()
411 tot_channels *= layers[idx].size; in edac_mc_alloc()
451 mci->layers = layer; in edac_mc_alloc()
452 memcpy(mci->layers, layers, sizeof(*layer) * n_layers); in edac_mc_alloc()
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A De7xxx_edac.c424 struct edac_mc_layer layers[2]; in e7xxx_probe1() local
443 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in e7xxx_probe1()
444 layers[0].size = E7XXX_NR_CSROWS; in e7xxx_probe1()
445 layers[0].is_virt_csrow = true; in e7xxx_probe1()
446 layers[1].type = EDAC_MC_LAYER_CHANNEL; in e7xxx_probe1()
447 layers[1].size = drc_chan + 1; in e7xxx_probe1()
448 layers[1].is_virt_csrow = false; in e7xxx_probe1()
449 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in e7xxx_probe1()
A Di82975x_edac.c467 struct edac_mc_layer layers[2]; in i82975x_probe1() local
540 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82975x_probe1()
541 layers[0].size = I82975X_NR_DIMMS; in i82975x_probe1()
542 layers[0].is_virt_csrow = true; in i82975x_probe1()
543 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82975x_probe1()
544 layers[1].size = I82975X_NR_CSROWS(chans); in i82975x_probe1()
545 layers[1].is_virt_csrow = false; in i82975x_probe1()
546 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in i82975x_probe1()
A Dbluefield_edac.c246 struct edac_mc_layer layers[1]; in bluefield_edac_mc_probe() local
273 layers[0].type = EDAC_MC_LAYER_SLOT; in bluefield_edac_mc_probe()
274 layers[0].size = dimm_count; in bluefield_edac_mc_probe()
275 layers[0].is_virt_csrow = true; in bluefield_edac_mc_probe()
277 mci = edac_mc_alloc(mc_idx, ARRAY_SIZE(layers), layers, sizeof(*priv)); in bluefield_edac_mc_probe()
A Di5400_edac.c1181 for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; in i5400_init_dimms()
1256 struct edac_mc_layer layers[3]; in i5400_probe1() local
1274 layers[0].type = EDAC_MC_LAYER_BRANCH; in i5400_probe1()
1275 layers[0].size = MAX_BRANCHES; in i5400_probe1()
1276 layers[0].is_virt_csrow = false; in i5400_probe1()
1278 layers[1].size = CHANNELS_PER_BRANCH; in i5400_probe1()
1279 layers[1].is_virt_csrow = false; in i5400_probe1()
1280 layers[2].type = EDAC_MC_LAYER_SLOT; in i5400_probe1()
1281 layers[2].size = DIMMS_PER_CHANNEL; in i5400_probe1()
1282 layers[2].is_virt_csrow = true; in i5400_probe1()
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A Dfsl_ddr_edac.c479 struct edac_mc_layer layers[2]; in fsl_mc_err_probe() local
488 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in fsl_mc_err_probe()
489 layers[0].size = 4; in fsl_mc_err_probe()
490 layers[0].is_virt_csrow = true; in fsl_mc_err_probe()
491 layers[1].type = EDAC_MC_LAYER_CHANNEL; in fsl_mc_err_probe()
492 layers[1].size = 1; in fsl_mc_err_probe()
493 layers[1].is_virt_csrow = false; in fsl_mc_err_probe()
494 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, in fsl_mc_err_probe()
A Die31200_edac.c400 struct edac_mc_layer layers[2]; in ie31200_probe1() local
420 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in ie31200_probe1()
421 layers[0].size = IE31200_DIMMS; in ie31200_probe1()
422 layers[0].is_virt_csrow = true; in ie31200_probe1()
423 layers[1].type = EDAC_MC_LAYER_CHANNEL; in ie31200_probe1()
424 layers[1].size = nr_channels; in ie31200_probe1()
425 layers[1].is_virt_csrow = false; in ie31200_probe1()
426 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in ie31200_probe1()
A Di7300_edac.c1024 struct edac_mc_layer layers[3]; in i7300_init_one() local
1042 layers[0].type = EDAC_MC_LAYER_BRANCH; in i7300_init_one()
1043 layers[0].size = MAX_BRANCHES; in i7300_init_one()
1044 layers[0].is_virt_csrow = false; in i7300_init_one()
1045 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i7300_init_one()
1046 layers[1].size = MAX_CH_PER_BRANCH; in i7300_init_one()
1047 layers[1].is_virt_csrow = true; in i7300_init_one()
1048 layers[2].type = EDAC_MC_LAYER_SLOT; in i7300_init_one()
1049 layers[2].size = MAX_SLOTS; in i7300_init_one()
1050 layers[2].is_virt_csrow = true; in i7300_init_one()
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/linux/drivers/media/dvb-frontends/
A Dtc90522.c201 int layers; in tc90522s_get_frontend() local
209 layers = 0; in tc90522s_get_frontend()
284 stats->len = layers; in tc90522s_get_frontend()
298 stats->len = layers; in tc90522s_get_frontend()
336 int layers; in tc90522t_get_frontend() local
352 layers = 0; in tc90522t_get_frontend()
364 layers++; in tc90522t_get_frontend()
377 layers++; in tc90522t_get_frontend()
389 layers++; in tc90522t_get_frontend()
444 stats->len = layers; in tc90522t_get_frontend()
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/linux/Documentation/devicetree/bindings/display/
A Dxylon,logicvc-display.yaml14 The Xylon LogiCVC is a display controller that supports multiple layers.
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
109 xylon,layers-configurable:
112 Configuration of layers' size, position and offset is enabled
115 layers:
187 The description of the display controller layers, containing layer
207 - layers
238 xylon,layers-configurable;
240 layers {
/linux/drivers/parisc/
A Dpdc_stable.c359 for (i = 0; i < 6 && devpath->layers[i]; i++) in pdcspath_layer_read()
360 out += sprintf(out, "%u ", devpath->layers[i]); in pdcspath_layer_read()
382 unsigned int layers[6]; /* device-specific info (ctlr#, unit#, ...) */ in pdcspath_layer_write() local
395 memset(&layers, 0, sizeof(layers)); in pdcspath_layer_write()
400 layers[0] = simple_strtoul(in, NULL, 10); in pdcspath_layer_write()
401 DPRINTK("%s: layer[0]: %d\n", __func__, layers[0]); in pdcspath_layer_write()
407 layers[i] = simple_strtoul(temp, NULL, 10); in pdcspath_layer_write()
408 DPRINTK("%s: layer[%d]: %d\n", __func__, i, layers[i]); in pdcspath_layer_write()
416 memcpy(&entry->devpath.layers, &layers, sizeof(layers)); in pdcspath_layer_write()

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