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/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_formats.c672 layout->total_size += layout->plane_size[i]; in _dpu_format_get_plane_sizes_ubwc()
696 layout->plane_pitch[0] = width * layout->format->bpp; in _dpu_format_get_plane_sizes_linear()
716 layout->plane_size[0] = layout->plane_pitch[0] * height; in _dpu_format_get_plane_sizes_linear()
717 layout->plane_size[1] = layout->plane_pitch[1] * in _dpu_format_get_plane_sizes_linear()
727 layout->plane_size[2] = layout->plane_size[1]; in _dpu_format_get_plane_sizes_linear()
728 layout->plane_pitch[2] = layout->plane_pitch[1]; in _dpu_format_get_plane_sizes_linear()
744 layout->total_size += layout->plane_size[i]; in _dpu_format_get_plane_sizes_linear()
817 layout->plane_addr[0] = base_addr + layout->plane_size[2]; in _dpu_format_populate_addrs_ubwc()
820 layout->plane_addr[1] = base_addr + layout->plane_size[0] in _dpu_format_populate_addrs_ubwc()
821 + layout->plane_size[2] + layout->plane_size[3]; in _dpu_format_populate_addrs_ubwc()
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A Ddpu_hw_sspp.c429 sspp->layout.format); in _dpu_hw_sspp_setup_scaler3()
481 ystride0 = (cfg->layout.plane_pitch[0]) | in dpu_hw_sspp_setup_rects()
482 (cfg->layout.plane_pitch[1] << 16); in dpu_hw_sspp_setup_rects()
484 (cfg->layout.plane_pitch[3] << 16); in dpu_hw_sspp_setup_rects()
496 ((cfg->layout.plane_pitch[0] << 16) & in dpu_hw_sspp_setup_rects()
499 ((cfg->layout.plane_pitch[2] << 16) & in dpu_hw_sspp_setup_rects()
527 cfg->layout.plane_addr[i]); in dpu_hw_sspp_setup_sourceaddress()
530 cfg->layout.plane_addr[0]); in dpu_hw_sspp_setup_sourceaddress()
532 cfg->layout.plane_addr[2]); in dpu_hw_sspp_setup_sourceaddress()
535 cfg->layout.plane_addr[0]); in dpu_hw_sspp_setup_sourceaddress()
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/linux/drivers/clk/at91/
A Dclk-programmable.c18 #define PROG_PRES(layout, pckr) ((pckr >> layout->pres_shift) & layout->pres_mask) argument
36 const struct clk_programmable_layout *layout = prog->layout; in clk_programmable_recalc_rate() local
42 if (layout->is_pres_direct) in clk_programmable_recalc_rate()
54 const struct clk_programmable_layout *layout = prog->layout; in clk_programmable_determine_rate() local
68 if (layout->is_pres_direct) { in clk_programmable_determine_rate()
106 const struct clk_programmable_layout *layout = prog->layout; in clk_programmable_set_parent() local
110 if (layout->have_slck_mck) in clk_programmable_set_parent()
131 const struct clk_programmable_layout *layout = prog->layout; in clk_programmable_get_parent() local
152 const struct clk_programmable_layout *layout = prog->layout; in clk_programmable_set_rate() local
175 layout->pres_mask << layout->pres_shift, in clk_programmable_set_rate()
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A Dclk-generated.c29 const struct clk_pcr_layout *layout; member
44 regmap_write(gck->regmap, gck->layout->offset, in clk_generated_set()
45 (gck->id & gck->layout->pid_mask)); in clk_generated_set()
48 gck->layout->cmd | enable, in clk_generated_set()
50 gck->layout->cmd | in clk_generated_set()
77 (gck->id & gck->layout->pid_mask)); in clk_generated_disable()
79 gck->layout->cmd | AT91_PMC_PCR_GCKEN, in clk_generated_disable()
80 gck->layout->cmd); in clk_generated_disable()
92 (gck->id & gck->layout->pid_mask)); in clk_generated_is_enabled()
305 (gck->id & gck->layout->pid_mask)); in clk_generated_startup()
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A Dclk-pll.c20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \ argument
21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask) argument
24 #define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1) argument
41 const struct clk_pll_layout *layout; member
59 const struct clk_pll_layout *layout = pll->layout; in clk_pll_prepare() local
73 mul = PLL_MUL(pllr, layout); in clk_pll_prepare()
90 ((pll->mul & layout->mul_mask) << layout->mul_shift)); in clk_pll_prepare()
128 const struct clk_pll_layout *layout = pll->layout; in clk_pll_get_best_div_mul() local
339 pll->layout = layout; in at91_clk_register_pll()
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A Dclk-peripheral.c39 const struct clk_pcr_layout *layout; member
170 (periph->id & periph->layout->pid_mask)); in clk_sam9x5_peripheral_set()
172 periph->layout->div_mask | periph->layout->cmd | in clk_sam9x5_peripheral_set()
175 periph->layout->cmd | enable); in clk_sam9x5_peripheral_set()
198 (periph->id & periph->layout->pid_mask)); in clk_sam9x5_peripheral_disable()
200 AT91_PMC_PCR_EN | periph->layout->cmd, in clk_sam9x5_peripheral_disable()
201 periph->layout->cmd); in clk_sam9x5_peripheral_disable()
216 (periph->id & periph->layout->pid_mask)); in clk_sam9x5_peripheral_is_enabled()
445 const struct clk_pcr_layout *layout, in at91_clk_register_sam9x5_peripheral() argument
479 if (layout->div_mask) in at91_clk_register_sam9x5_peripheral()
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A Dclk-master.c90 const struct clk_master_layout *layout = master->layout; in clk_master_div_recalc_rate() local
99 mckr &= layout->mask; in clk_master_div_recalc_rate()
124 mckr &= master->layout->mask; in clk_master_div_save_context()
145 mckr &= master->layout->mask; in clk_master_div_restore_context()
192 mckr &= master->layout->mask; in clk_master_div_set()
469 val &= master->layout->mask; in clk_master_pres_recalc_rate()
505 val &= master->layout->mask; in clk_master_pres_save_context()
529 val &= master->layout->mask; in clk_master_pres_restore_context()
599 master->layout = layout; in at91_clk_register_master_internal()
610 mckr &= layout->mask; in at91_clk_register_master_internal()
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A Dclk-sam9x60-pll.c35 const struct clk_pll_layout *layout; member
96 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; in sam9x60_frac_pll_set()
97 cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift; in sam9x60_frac_pll_set()
263 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; in sam9x60_frac_pll_set_rate_chg()
264 cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift; in sam9x60_frac_pll_set_rate_chg()
367 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_set()
400 core->layout->endiv_mask, 0); in sam9x60_div_pll_unprepare()
513 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_set_rate_chg()
569 cdiv = (val & core.layout->div_mask) >> core.layout->div_shift; in sam9x60_div_pll_notifier_fn()
644 frac->core.layout = layout; in sam9x60_clk_register_frac_pll()
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A Dpmc.h145 const struct clk_pcr_layout *layout,
176 const struct clk_master_layout *layout,
183 const struct clk_master_layout *layout,
199 const struct clk_pcr_layout *layout,
207 const struct clk_pll_layout *layout,
217 const struct clk_pll_layout *layout, u32 flags,
225 const struct clk_pll_layout *layout, u32 flags);
230 const struct clk_programmable_layout *layout,
/linux/drivers/gpio/
A Dgpio-creg-snps.c33 const struct creg_layout *layout = hcg->layout; in creg_gpio_set() local
38 value = val ? hcg->layout->on[offset] : hcg->layout->off[offset]; in creg_gpio_set()
42 reg_shift += layout->bit_per_gpio[i] + layout->shift[i]; in creg_gpio_set()
62 const struct creg_layout *layout = hcg->layout; in creg_gpio_validate_pg() local
64 if (layout->bit_per_gpio[i] < 1 || layout->bit_per_gpio[i] > 8) in creg_gpio_validate_pg()
68 if (GENMASK(31, layout->bit_per_gpio[i]) & layout->on[i]) in creg_gpio_validate_pg()
72 if (GENMASK(31, layout->bit_per_gpio[i]) & layout->off[i]) in creg_gpio_validate_pg()
75 if (layout->on[i] == layout->off[i]) in creg_gpio_validate_pg()
87 if (hcg->layout->ngpio < 1 || hcg->layout->ngpio > MAX_GPIO) in creg_gpio_validate()
99 reg_len += hcg->layout->shift[i] + hcg->layout->bit_per_gpio[i]; in creg_gpio_validate()
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/linux/include/linux/mfd/syscon/
A Datmel-smc.h19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
26 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8)
33 #define ATMEL_HSMC_MODE(layout, cs) \ argument
34 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x10)
64 #define ATMEL_HSMC_TIMINGS(layout, cs) \ argument
65 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0xc)
/linux/drivers/gpu/drm/atmel-hlcdc/
A Datmel_hlcdc_plane.c338 if (desc->layout.size) in atmel_hlcdc_plane_update_pos_and_size()
343 if (desc->layout.memsize) in atmel_hlcdc_plane_update_pos_and_size()
345 desc->layout.memsize, in atmel_hlcdc_plane_update_pos_and_size()
349 if (desc->layout.pos) in atmel_hlcdc_plane_update_pos_and_size()
528 layout = &primary->layer.desc->layout; in atmel_hlcdc_plane_prepare_disc_area()
529 if (!layout->disc_pos || !layout->disc_size) in atmel_hlcdc_plane_prepare_disc_area()
582 layout = &plane->layer.desc->layout; in atmel_hlcdc_plane_update_disc_area()
583 if (!layout->disc_pos || !layout->disc_size) in atmel_hlcdc_plane_update_disc_area()
701 if (!desc->layout.size && in atmel_hlcdc_plane_atomic_check()
785 if (desc->layout.xstride[0] && desc->layout.pstride[0]) { in atmel_hlcdc_plane_init_properties()
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A Datmel_hlcdc_dc.c40 .layout = {
70 .layout = {
86 .layout = {
105 .layout = {
129 .layout = {
163 .layout = {
179 .layout = {
198 .layout = {
217 .layout = {
245 .layout = {
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/linux/Documentation/filesystems/nfs/
A Dpnfs.rst17 Each nfs_inode may hold a pointer to a cache of these layout
18 segments in nfsi->layout, of type struct pnfs_layout_hdr.
26 the reference count, as the layout is kept around by the lseg that
33 layout driver type. The device ids are held in a RCU cache (struct
62 layout drivers
65 PNFS utilizes what is called layout drivers. The STD defines 4 basic
69 different layout types.
71 Files-layout-driver code is in: fs/nfs/filelayout/.. directory
72 Blocks-layout-driver code is in: fs/nfs/blocklayout/.. directory
75 blocks-layout setup
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/linux/drivers/mfd/
A Datmel-smc.c266 const struct atmel_hsmc_reg_layout *layout, in atmel_hsmc_cs_conf_apply() argument
269 regmap_write(regmap, ATMEL_HSMC_SETUP(layout, cs), conf->setup); in atmel_hsmc_cs_conf_apply()
270 regmap_write(regmap, ATMEL_HSMC_PULSE(layout, cs), conf->pulse); in atmel_hsmc_cs_conf_apply()
271 regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle); in atmel_hsmc_cs_conf_apply()
272 regmap_write(regmap, ATMEL_HSMC_TIMINGS(layout, cs), conf->timings); in atmel_hsmc_cs_conf_apply()
273 regmap_write(regmap, ATMEL_HSMC_MODE(layout, cs), conf->mode); in atmel_hsmc_cs_conf_apply()
307 const struct atmel_hsmc_reg_layout *layout, in atmel_hsmc_cs_conf_get() argument
310 regmap_read(regmap, ATMEL_HSMC_SETUP(layout, cs), &conf->setup); in atmel_hsmc_cs_conf_get()
311 regmap_read(regmap, ATMEL_HSMC_PULSE(layout, cs), &conf->pulse); in atmel_hsmc_cs_conf_get()
312 regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle); in atmel_hsmc_cs_conf_get()
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/linux/drivers/md/
A Draid5.h763 static inline int algorithm_valid_raid5(int layout) in algorithm_valid_raid5() argument
765 return (layout >= 0) && in algorithm_valid_raid5()
766 (layout <= 5); in algorithm_valid_raid5()
768 static inline int algorithm_valid_raid6(int layout) in algorithm_valid_raid6() argument
770 return (layout >= 0 && layout <= 5) in algorithm_valid_raid6()
772 (layout >= 8 && layout <= 10) in algorithm_valid_raid6()
774 (layout >= 16 && layout <= 20); in algorithm_valid_raid6()
777 static inline int algorithm_is_DDF(int layout) in algorithm_is_DDF() argument
779 return layout >= 8 && layout <= 10; in algorithm_is_DDF()
A Ddm-raid.c530 return layout & 0xFF; in __raid10_near_copies()
542 return !!(layout & RAID10_OFFSET); in __is_raid10_offset()
548 return !__is_raid10_offset(layout) && __raid10_near_copies(layout) > 1; in __is_raid10_near()
554 return !__is_raid10_offset(layout) && __raid10_far_copies(layout) > 1; in __is_raid10_far()
566 if (__is_raid10_offset(layout)) in raid10_md_layout_to_format()
594 return max(__raid10_near_copies(layout), __raid10_far_copies(layout)); in raid10_md_layout_to_copies()
645 return __is_raid10_far(layout); in __got_raid10()
674 (__got_raid10(rtp, layout) || rtp->algorithm == layout)) in get_raid_type_by_ll()
1950 __le32 layout; member
2118 sb->layout = cpu_to_le32(mddev->layout); in super_sync()
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/linux/sound/aoa/fabrics/
A Dlayout.c62 struct layout { struct
271 static struct layout layouts[] = {
564 struct layout *l; in find_layout_by_id()
577 struct layout *l; in find_layout_by_device()
611 struct layout *layout; member
1000 struct layout *layout = NULL; in aoa_fabric_layout_probe() local
1025 if (!layout) { in aoa_fabric_layout_probe()
1037 ldev->layout = layout; in aoa_fabric_layout_probe()
1039 switch (layout->layout_id) { in aoa_fabric_layout_probe()
1063 if (ldev->layout->busname) { in aoa_fabric_layout_probe()
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A DMakefile2 snd-aoa-fabric-layout-objs += layout.o
4 obj-$(CONFIG_SND_AOA_FABRIC_LAYOUT) += snd-aoa-fabric-layout.o
/linux/drivers/comedi/drivers/
A Dcb_pcidas64.c682 .layout = LAYOUT_64XX,
698 .layout = LAYOUT_64XX,
714 .layout = LAYOUT_64XX,
730 .layout = LAYOUT_64XX,
746 .layout = LAYOUT_64XX,
761 .layout = LAYOUT_60XX,
777 .layout = LAYOUT_60XX,
792 .layout = LAYOUT_60XX,
808 .layout = LAYOUT_60XX,
824 .layout = LAYOUT_60XX,
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/linux/drivers/input/keyboard/
A Dsunkbd.c70 volatile s8 layout; member
93 if (sunkbd->layout == -1) { in sunkbd_interrupt()
94 sunkbd->layout = data; in sunkbd_interrupt()
108 sunkbd->layout = -1; in sunkbd_interrupt()
190 sunkbd->layout = -2; in sunkbd_initialize()
193 sunkbd->layout >= 0, HZ / 4); in sunkbd_initialize()
194 if (sunkbd->layout < 0) in sunkbd_initialize()
196 if (sunkbd->layout & SUNKBD_LAYOUT_5_MASK) in sunkbd_initialize()
/linux/fs/ceph/
A Dioctl.c117 req->r_args.setlayout.layout.fl_stripe_unit = in ceph_ioctl_set_layout()
119 req->r_args.setlayout.layout.fl_stripe_count = in ceph_ioctl_set_layout()
121 req->r_args.setlayout.layout.fl_object_size = in ceph_ioctl_set_layout()
123 req->r_args.setlayout.layout.fl_pg_pool = cpu_to_le32(l.data_pool); in ceph_ioctl_set_layout()
161 req->r_args.setlayout.layout.fl_stripe_unit = in ceph_ioctl_set_layout_policy()
163 req->r_args.setlayout.layout.fl_stripe_count = in ceph_ioctl_set_layout_policy()
165 req->r_args.setlayout.layout.fl_object_size = in ceph_ioctl_set_layout_policy()
167 req->r_args.setlayout.layout.fl_pg_pool = in ceph_ioctl_set_layout_policy()
A Dutil.c11 int ceph_file_layout_is_valid(const struct ceph_file_layout *layout) in ceph_file_layout_is_valid() argument
13 __u32 su = layout->stripe_unit; in ceph_file_layout_is_valid()
14 __u32 sc = layout->stripe_count; in ceph_file_layout_is_valid()
15 __u32 os = layout->object_size; in ceph_file_layout_is_valid()
/linux/drivers/gpu/drm/nouveau/dispnv50/
A Dhead917d.c91 NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | in head917d_curs_set()
107 case 32: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32; break; in head917d_curs_layout()
108 case 64: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64; break; in head917d_curs_layout()
109 case 128: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128; break; in head917d_curs_layout()
110 case 256: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256; break; in head917d_curs_layout()
/linux/drivers/net/dsa/
A Dbcm_sf2_cfp.c124 if (layout[i] != 0) in bcm_sf2_get_num_udf_slices()
158 const struct cfp_udf_layout *layout, in bcm_sf2_cfp_udf_set() argument
161 u32 offset = layout->udfs[slice_num].base_offset; in bcm_sf2_cfp_udf_set()
353 const struct cfp_udf_layout *layout; in bcm_sf2_cfp_ipv4_rule_set() local
402 layout = &udf_tcpip4_layout; in bcm_sf2_cfp_ipv4_rule_set()
404 slice_num = bcm_sf2_get_slice_number(layout, 0); in bcm_sf2_cfp_ipv4_rule_set()
413 bcm_sf2_cfp_udf_set(priv, layout, slice_num); in bcm_sf2_cfp_ipv4_rule_set()
635 const struct cfp_udf_layout *layout; in bcm_sf2_cfp_ipv6_rule_set() local
663 layout = &udf_tcpip6_layout; in bcm_sf2_cfp_ipv6_rule_set()
712 bcm_sf2_cfp_udf_set(priv, layout, slice_num); in bcm_sf2_cfp_ipv6_rule_set()
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