| /linux/kernel/sched/ |
| A D | loadavg.c | 72 void get_avenrun(unsigned long *loads, unsigned long offset, int shift) in get_avenrun() argument
74 loads[0] = (avenrun[0] + offset) << shift; in get_avenrun()
75 loads[1] = (avenrun[1] + offset) << shift; in get_avenrun()
76 loads[2] = (avenrun[2] + offset) << shift; in get_avenrun()
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| /linux/tools/testing/selftests/net/ |
| A D | devlink_port_split.py | 60 ports = json.loads(stdout)['port']
82 values = list(json.loads(stdout)['port'].values())[0]
100 values = list(json.loads(stdout)['port'].values())[0]
243 devs = json.loads(stdout)['dev']
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| /linux/arch/powerpc/perf/ |
| A D | power9-pmu.c | 174 GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS);
178 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
182 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
185 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
188 CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);
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| A D | power8-pmu.c | 134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
139 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
143 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
149 CACHE_EVENT_ATTR(branch-loads, PM_BRU_FIN);
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| A D | power10-pmu.c | 127 GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
138 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
141 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
146 CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);
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| /linux/tools/perf/Documentation/ |
| A D | perf-mem.txt | 19 right set of options to display a memory access profile. By default, loads
20 and stores are sampled. Use the -t option to limit to loads or stores.
88 Specify desired latency for loads event. (x86 only)
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| A D | perf-c2c.txt | 52 Configure mem-loads latency. (x86 only)
138 cpu/mem-loads,ldlat=30/P
143 cpu/mem-loads/
186 Total loads
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| /linux/arch/alpha/lib/ |
| A D | ev6-copy_user.S | 64 EXI( ldbu $1,0($17) ) # .. .. .. L : Keep loads separate from stores
116 EXI ( ldbu $2,0($17) ) # .. .. .. L : No loads in the same quad
203 EXI ( ldbu $2,0($17) ) # .. .. .. L : No loads in the same quad
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| /linux/Documentation/x86/ |
| A D | tsx_async_abort.rst | 13 case certain loads may speculatively pass invalid data to dependent operations
15 Synchronization Extensions (TSX) transaction. This includes loads with no
16 fault or assist condition. Such loads may speculatively expose stale data from
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| /linux/Documentation/core-api/ |
| A D | refcount-vs-atomic.rst | 41 A strong (full) memory ordering guarantees that all prior loads and
49 A RELEASE memory ordering guarantees that all prior loads and
57 An ACQUIRE memory ordering guarantees that all post loads and
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| /linux/include/uapi/linux/ |
| A D | sysinfo.h | 10 __kernel_ulong_t loads[3]; /* 1, 5, and 15 minute load averages */ member
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| /linux/Documentation/ |
| A D | memory-barriers.txt | 388 to have any effect on loads.
409 or overlapping loads.
702 load from 'a' with other loads from 'a'. Without the WRITE_ONCE(),
879 Not prior loads against later loads, nor prior stores against
882 later loads, smp_mb().
1025 loads. Consider the following sequence of events:
1107 subsequent loads +-------+ | |
1754 The compiler can also invent loads. These are usually less
1757 invented loads.
2208 the other hand, a wakeup does not occur, both loads might see 0.
[all …]
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| /linux/include/linux/sched/ |
| A D | loadavg.h | 16 extern void get_avenrun(unsigned long *loads, unsigned long offset, int shift);
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| /linux/tools/perf/util/ |
| A D | parse-events.l | 364 mem-loads |
365 mem-loads-aux |
379 load|loads|read |
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| /linux/tools/memory-model/Documentation/ |
| A D | control-dependencies.txt | 42 fuse the load from "a" with other loads. Without the WRITE_ONCE(),
219 (*) Control dependencies can order prior loads against later stores.
221 Not prior loads against later loads, nor prior stores against
224 stores and later loads, smp_mb().
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| A D | explanation.txt | 79 code to run in such a way that the loads will indeed obtain the
196 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
197 it, as loads can obtain values only from earlier stores.
271 X: P1 loads 1 from flag executes before
272 Y: P1 loads 0 from buf executes before
292 Read events correspond to loads from shared memory, such as
784 smp_rmb() forces the CPU to execute all po-earlier loads
785 before any po-later loads;
933 CPU 0 loads x obtaining 13;
934 CPU 1 loads x obtaining 13;
[all …]
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| A D | access-marking.txt | 38 using READ_ONCE() for loads and WRITE_ONCE() for stores is usually
64 1. Data-racy loads from shared variables whose values are used only
95 In theory, plain C-language loads can also be used for this use case.
119 In theory, plain C-language loads can also be used for this use case.
130 that data_race() loads are subject to load fusing, which can result in
140 In theory, plain C-language loads can also be used for this use case.
183 5. Any other loads for which there is not supposed to be a concurrent
187 loads nor concurrent stores to that same variable.
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| A D | recipes.txt | 46 tearing, load/store fusing, and invented loads and stores.
204 and another CPU execute a pair of loads from this same pair of variables,
311 smp_rmb() macro orders prior loads against later loads. Therefore, if
354 second, while another CPU loads from the second variable and then stores
475 that one CPU first stores to one variable and then loads from a second,
476 while another CPU stores to the second variable and then loads from the
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| /linux/arch/mips/kernel/ |
| A D | mips-r2-to-r6-emul.c | 1274 MIPS_R2_STATS(loads); in mipsr2_decoder()
1348 MIPS_R2_STATS(loads); in mipsr2_decoder()
1608 MIPS_R2_STATS(loads); in mipsr2_decoder()
1727 MIPS_R2_STATS(loads); in mipsr2_decoder()
2267 (unsigned long)__this_cpu_read(mipsr2emustats.loads), in mipsr2_emul_show()
2268 (unsigned long)__this_cpu_read(mipsr2bdemustats.loads)); in mipsr2_emul_show()
2324 __this_cpu_write((mipsr2emustats).loads, 0); in mipsr2_clear_show()
2325 __this_cpu_write((mipsr2bdemustats).loads, 0); in mipsr2_clear_show()
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| /linux/kernel/debug/kdb/ |
| A D | kdb_main.c | 2482 val->loads[0] = avenrun[0]; in kdb_sysinfo()
2483 val->loads[1] = avenrun[1]; in kdb_sysinfo()
2484 val->loads[2] = avenrun[2]; in kdb_sysinfo()
2521 LOAD_INT(val.loads[0]), LOAD_FRAC(val.loads[0]), in kdb_summary()
2522 LOAD_INT(val.loads[1]), LOAD_FRAC(val.loads[1]), in kdb_summary()
2523 LOAD_INT(val.loads[2]), LOAD_FRAC(val.loads[2])); in kdb_summary()
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| /linux/Documentation/devicetree/bindings/remoteproc/ |
| A D | st,stm32-rproc.yaml | 10 This document defines the binding for the remoteproc component that loads and
114 If defined, when remoteproc is probed, it loads the default firmware and
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| /linux/Documentation/devicetree/bindings/mfd/ |
| A D | x-powers,axp152.yaml | 280 mixed PWM/PFM mode, using PFM under light loads and
281 switching to PWM for heavier loads. Forcing PWM mode
282 trades efficiency under light loads for lower output
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| /linux/arch/mips/include/asm/ |
| A D | mips-r2-to-r6-emul.h | 22 u64 loads; member
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| /linux/Documentation/devicetree/bindings/sound/ |
| A D | richtek,rt9120.yaml | 14 delivering 2*20W into 8 Ohm BTL speaker loads. It supports the wide input
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| /linux/arch/powerpc/lib/ |
| A D | memcpy_64.S | 115 ld r9,0(r4) # 3+2n loads, 2+2n stores
127 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
|