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Searched refs:lsl (Results 1 – 25 of 101) sorted by relevance

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/linux/arch/arm/lib/
A Dio-writesw-armv3.S25 orr r3, r3, r3, lsl #16
43 mov ip, r3, lsl #16
48 orr ip, ip, ip, lsl #16
51 mov ip, r4, lsl #16
56 orr ip, ip, ip, lsl #16
59 mov ip, r5, lsl #16
67 mov ip, r6, lsl #16
86 mov ip, r3, lsl #16
94 mov ip, r4, lsl #16
107 mov ip, r3, lsl #16
[all …]
A Dbitops.h14 add r1, r1, r0, lsl #2 @ Get word offset
20 mov r3, r2, lsl r3
39 add r1, r1, r0, lsl #2 @ Get word offset
40 mov r3, r2, lsl r3 @ create mask
69 mov r3, r3, lsl r2
71 ldr r2, [r1, r0, lsl #2]
73 str r2, [r1, r0, lsl #2]
96 ldr r2, [r1, r0, lsl #2]!
98 tst r2, r0, lsl r3
99 \instr r2, r2, r0, lsl r3
A Dio-readsw-armv3.S36 orr ip, ip, ip, lsl #8
45 orr r3, r3, r4, lsl #16
50 orr r4, r4, r5, lsl #16
55 orr r5, r5, r6, lsl #16
60 orr r6, r6, lr, lsl #16
76 orr r3, r3, r4, lsl #16
81 orr r4, r4, r5, lsl #16
91 orr r3, r3, r4, lsl #16
A Dio-readsw-armv4.S12 orr \rd, \hw1, \hw2, lsl #16
14 orr \rd, \hw2, \hw1, lsl #16
18 .Linsw_align: movs ip, r1, lsl #31
68 .Lno_insw_4: movs r2, r2, lsl #31
85 #define pull_hbyte1 lsl #24
89 #define push_hbyte0 lsl #24
106 _BE_ONLY_( mov ip, ip, lsl #24 )
111 orr ip, ip, r3, lsl #8
A Ddiv64.S69 mov ip, ip, lsl yl
70 mov yl, r4, lsl yl
78 movcc yl, yl, lsl #1
79 movcc ip, ip, lsl #1
104 4: movs xl, xl, lsl #1
127 mov xl, xl, lsl xh
132 7: movs xl, xl, lsl #1
180 ARM( orr yl, yl, xh, lsl ip )
181 THUMB( lsl xh, xh, ip )
183 mov xh, xl, lsl ip
A Dmuldi3.S32 bic xl, xl, ip, lsl #16
33 bic yl, yl, yh, lsl #16
38 adds xl, xl, yh, lsl #16
40 adds xl, xl, ip, lsl #16
A Dlib1funcs.S48 mov \divisor, \divisor, lsl \result
49 mov \curbit, \curbit, lsl \result
59 moveq \divisor, \divisor, lsl #3
69 movlo \divisor, \divisor, lsl #4
70 movlo \curbit, \curbit, lsl #4
77 movlo \divisor, \divisor, lsl #1
78 movlo \curbit, \curbit, lsl #1
144 mov \divisor, \divisor, lsl \order
156 movlo \divisor, \divisor, lsl #4
164 movlo \divisor, \divisor, lsl #1
A Dashldi3.S45 movmi ah, ah, lsl r2
46 movpl ah, al, lsl r3
50 mov al, al, lsl r2
A Dio-writesw-armv4.S22 .Loutsw_align: movs ip, r1, lsl #31
55 .Lno_outsw_4: movs r2, r2, lsl #31
67 #define pull_hbyte0 lsl #8
71 #define push_hbyte1 lsl #8
/linux/drivers/scsi/arm/
A Dacornscsi-io.S31 orr r3, r3, r4, lsl #16
33 orr r4, r4, r6, lsl #16
36 orr r5, r5, r6, lsl #16
38 orr r6, r6, ip, lsl #16
82 mov r3, r4, lsl #16
86 mov r5, r6, lsl #16
91 mov r3, ip, lsl #16
95 mov ip, lr, lsl #16
106 mov r3, r4, lsl #16
110 mov r5, r6, lsl #16
[all …]
/linux/arch/arm/boot/compressed/
A Dll_char_wr.S40 mov r1, r1, lsl #3
56 add r0, r0, r5, lsl #3 @ Move to bottom of character
65 ldr r7, [lr, r7, lsl #2]
70 ldr r7, [lr, r7, lsl #2]
84 ldr ip, [lr, ip, lsl #2]
87 ldr ip, [lr, ip, lsl #2] @ avoid r4
94 ldr ip, [lr, ip, lsl #2]
97 ldr ip, [lr, ip, lsl #2] @ avoid r4
/linux/arch/arm64/lib/
A Dtishift.S16 lsl x1, x1, x2
18 lsl x2, x0, x2
26 lsl x1, x0, x1
39 lsl x3, x1, x3
61 lsl x3, x1, x3
A Dstrncmp.S84 lsl limit, limit, #3 /* Bits -> bytes. */
89 lsl mask, mask, limit
109 lsl data1, data1, pos
110 lsl data2, data2, pos
141 lsl data1, data1, pos
142 lsl data2, data2, pos
159 neg tmp3, count, lsl #3 /* 64 - bits(bytes beyond align). */
165 lsl tmp2, tmp2, tmp3 /* Shift (count & 63). */
A Dstrcmp.S76 lsl data1, data1, pos
77 lsl data2, data2, pos
108 lsl data1, data1, pos
109 lsl data2, data2, pos
123 lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
130 lsl tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
/linux/arch/arm/mm/
A Dabort-lv4t.S68 and r9, r8, r7, lsl #1
70 and r9, r8, r7, lsl #2
72 and r9, r8, r7, lsl #3
80 subne r7, r7, r6, lsl #2 @ Undo increment
81 addeq r7, r7, r6, lsl #2 @ Undo decrement
95 ldreq r6, [r2, r9, lsl #2] @ { load Rm value }
110 movs r6, r8, lsl #20 @ Get offset
127 ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
136 mov r6, r6, lsl r9 @ 0: LSL #!0
217 subne r7, r7, r6, lsl #2 @ decrement SP if POP
[all …]
A Dtlb-v7.S43 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
44 mov r1, r1, lsl #PAGE_SHIFT
72 mov r0, r0, lsl #PAGE_SHIFT
73 mov r1, r1, lsl #PAGE_SHIFT
A Dtlb-v6.S41 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
42 mov r1, r1, lsl #PAGE_SHIFT
71 mov r0, r0, lsl #PAGE_SHIFT
72 mov r1, r1, lsl #PAGE_SHIFT
/linux/arch/arm/kernel/
A Dphys2virt.S42 teq r3, r0, lsl #21 @ must be 2 MiB aligned
64 @ lsl <reg>, #21
68 @ lsl <reg>, #21
72 @ lsl <reg>, #21
144 @ phys-to-virt: sub <VA>, <PA>, #offset<31:24>, lsl #24
145 @ sub <VA>, <PA>, #offset<23:16>, lsl #16
148 @ add <PA>, <VA>, #offset<23:16>, lsl #16
151 @ adds <PAlo>, <VA>, <reg>, lsl #20
195 orreq ip, ip, r6, lsl #4 @ MOVW -> mask in offset bits 31-24
204 orreq ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24
[all …]
/linux/arch/arm/include/asm/
A Dassembler.h34 #define lspush lsl
35 #define get_byte_0 lsl #0
39 #define put_byte_0 lsl #0
40 #define put_byte_1 lsl #8
41 #define put_byte_2 lsl #16
42 #define put_byte_3 lsl #24
44 #define lspull lsl
49 #define get_byte_3 lsl #0
50 #define put_byte_0 lsl #24
51 #define put_byte_1 lsl #16
[all …]
/linux/arch/m68k/math-emu/
A Dfp_movem.S157 3: lsl.b #1,%d1
164 lsl.w #1,%d2
165 lsl.l #7,%d2
166 lsl.l #8,%d2
176 4: lsl.b #1,%d1
307 lsl.l #5,%d1
312 3: lsl.b #1,%d1
320 lsl.l #5,%d1
331 3: lsl.b #1,%d1
341 4: lsl.b #1,%d1
A Dfp_util.S131 lsl.l #8,%d0 | shift mantissa
168 lsl.l #8,%d0 | shift high mantissa
169 lsl.l #3,%d0
182 lsl.l #8,%d0
183 lsl.l #3,%d0
/linux/arch/arm/crypto/
A Dsha1-armv4-large.S87 orr r9,r9,r10,lsl#8
89 orr r9,r9,r11,lsl#16
91 orr r9,r9,r12,lsl#24
112 orr r9,r9,r10,lsl#8
114 orr r9,r9,r11,lsl#16
116 orr r9,r9,r12,lsl#24
137 orr r9,r9,r10,lsl#8
139 orr r9,r9,r11,lsl#16
162 orr r9,r9,r10,lsl#8
187 orr r9,r9,r10,lsl#8
[all …]
/linux/arch/arm/mach-tegra/
A Dsleep.h54 movne \rd, \rd, lsl #3
63 movne \rd, \rd, lsl #3
98 moveq \tmp1, \tmp1, lsl #2
100 moveq \tmp2, \tmp2, lsl \tmp1
/linux/arch/arm64/include/asm/
A Dassembler.h174 orr \rd, \lbits, \hbits, lsl #32
291 movk \reg, #0, lsl #16
292 movk \reg, #0, lsl #32
293 movk \reg, #0, lsl #48
307 lsl \reg, \reg, \tmp // actual cache line size
317 lsl \reg, \reg, \tmp // actual cache line size
328 lsl \reg, \reg, \tmp // actual cache line size
338 lsl \reg, \reg, \tmp // actual cache line size
641 lsl \phys, \phys, #16
A Dkvm_mmu.h70 add \reg, \reg, #0, lsl 12 /* insert the top 12 bits of the tag */
102 movk \tmp, #0, lsl #16
103 movk \tmp, #0, lsl #32
104 movk \tmp, #0, lsl #48

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