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Searched refs:mask2 (Results 1 – 25 of 59) sorted by relevance

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/linux/drivers/soc/fsl/qe/
A Dgpio.c249 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); in qe_pin_set_dedicated() local
256 qe_clrsetbits_be32(&regs->cpdir2, mask2, in qe_pin_set_dedicated()
257 sregs->cpdir2 & mask2); in qe_pin_set_dedicated()
258 qe_clrsetbits_be32(&regs->cppar2, mask2, in qe_pin_set_dedicated()
259 sregs->cppar2 & mask2); in qe_pin_set_dedicated()
261 qe_clrsetbits_be32(&regs->cpdir1, mask2, in qe_pin_set_dedicated()
262 sregs->cpdir1 & mask2); in qe_pin_set_dedicated()
263 qe_clrsetbits_be32(&regs->cppar1, mask2, in qe_pin_set_dedicated()
264 sregs->cppar1 & mask2); in qe_pin_set_dedicated()
/linux/fs/orangefs/
A Dorangefs-debugfs.c64 __u64 mask2; member
475 c_mask.mask2); in orangefs_debug_write()
562 (unsigned long long *)&(cdm_array[i].mask2)); in orangefs_prepare_cdm_array()
773 (mask->mask2 & cdm_array[index].mask2)) { in do_c_string()
817 (c_mask->mask2 == cdm_array[client_all_index].mask2)) { in check_amalgam_keyword()
824 (c_mask->mask2 == cdm_array[client_verbose_index].mask2)) { in check_amalgam_keyword()
893 (**sane_mask).mask2 = (**sane_mask).mask2 | cdm_array[i].mask2; in do_c_mask()
918 client_debug_mask.mask2 = mask2_info.mask2_value; in orangefs_debugfs_new_client_mask()
924 (unsigned long long)client_debug_mask.mask2); in orangefs_debugfs_new_client_mask()
/linux/sound/pci/ice1712/
A Dwm8776.c140 .mask2 = WM8776_DACVOL_MASK,
150 .mask2 = WM8776_DAC_PL_RR,
166 .mask2 = WM8776_HPVOL_MASK,
184 .mask2 = WM8776_VOL_HPZCEN,
211 .mask2 = WM8776_PHASE_INVERTR,
227 .mask2 = WM8776_ADC_GAIN_MASK,
237 .mask2 = WM8776_ADC_MUTER,
493 val2 >>= __ffs(wm->ctl[n].mask2); in snd_wm8776_ctl_get()
532 val &= ~wm->ctl[n].mask2; in snd_wm8776_ctl_put()
533 val |= regval2 << __ffs(wm->ctl[n].mask2); in snd_wm8776_ctl_put()
[all …]
A Dwm8766.c37 .mask2 = WM8766_VOL_MASK,
48 .mask2 = WM8766_VOL_MASK,
59 .mask2 = WM8766_VOL_MASK,
218 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; in snd_wm8766_ctl_get()
219 val2 >>= __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_get()
258 val &= ~wm->ctl[n].mask2; in snd_wm8766_ctl_put()
259 val |= regval2 << __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_put()
265 val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; in snd_wm8766_ctl_put()
266 val |= regval2 << __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_put()
/linux/arch/mips/sgi-ip22/
A Dip22-int.c114 u8 mask2; in indy_local0_irqdispatch() local
118 mask2 = sgint->vmeistat & sgint->cmeimask0; in indy_local0_irqdispatch()
119 irq = lc2msk_to_irqnr[mask2]; in indy_local0_irqdispatch()
136 u8 mask2; in indy_local1_irqdispatch() local
140 mask2 = sgint->vmeistat & sgint->cmeimask1; in indy_local1_irqdispatch()
141 irq = lc3msk_to_irqnr[mask2]; in indy_local1_irqdispatch()
/linux/drivers/gpu/drm/amd/display/dc/
A Ddc_helper.c310 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) in generic_reg_get2() argument
314 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get2()
320 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get3() argument
325 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get3()
332 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get4() argument
338 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get4()
346 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get5() argument
353 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get5()
362 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get6() argument
380 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get7() argument
[all …]
/linux/drivers/net/wireless/ath/ath9k/
A Dar9002_mac.c36 u32 mask2 = 0; in ar9002_hw_get_isr() local
67 mask2 |= ATH9K_INT_TIM; in ar9002_hw_get_isr()
69 mask2 |= ATH9K_INT_DTIM; in ar9002_hw_get_isr()
71 mask2 |= ATH9K_INT_DTIMSYNC; in ar9002_hw_get_isr()
73 mask2 |= ATH9K_INT_CABEND; in ar9002_hw_get_isr()
75 mask2 |= ATH9K_INT_GTT; in ar9002_hw_get_isr()
77 mask2 |= ATH9K_INT_CST; in ar9002_hw_get_isr()
79 mask2 |= ATH9K_INT_TSFOOR; in ar9002_hw_get_isr()
134 *masked |= mask2; in ar9002_hw_get_isr()
A Dar9003_mac.c186 u32 mask2 = 0; in ar9003_hw_get_isr() local
216 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> in ar9003_hw_get_isr()
218 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> in ar9003_hw_get_isr()
220 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> in ar9003_hw_get_isr()
222 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> in ar9003_hw_get_isr()
224 mask2 |= ((isr2 & AR_ISR_S2_GTT) << in ar9003_hw_get_isr()
226 mask2 |= ((isr2 & AR_ISR_S2_CST) << in ar9003_hw_get_isr()
228 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> in ar9003_hw_get_isr()
230 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> in ar9003_hw_get_isr()
302 *masked |= mask2; in ar9003_hw_get_isr()
A Dmac.c911 u32 mask, mask2; in ath9k_hw_set_interrupts() local
928 mask2 = 0; in ath9k_hw_set_interrupts()
972 mask2 |= AR_IMR_S2_TIM; in ath9k_hw_set_interrupts()
974 mask2 |= AR_IMR_S2_DTIM; in ath9k_hw_set_interrupts()
976 mask2 |= AR_IMR_S2_DTIMSYNC; in ath9k_hw_set_interrupts()
978 mask2 |= AR_IMR_S2_CABEND; in ath9k_hw_set_interrupts()
980 mask2 |= AR_IMR_S2_TSFOOR; in ath9k_hw_set_interrupts()
986 mask2 |= AR_IMR_S2_GTT; in ath9k_hw_set_interrupts()
988 mask2 |= AR_IMR_S2_CST; in ath9k_hw_set_interrupts()
994 mask2 |= AR_IMR_S2_BB_WATCHDOG; in ath9k_hw_set_interrupts()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
A Dirq_service_dcn30.c222 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
232 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
234 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
236 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
246 reg2 ## __ ## mask2 ## _MASK,\
248 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
A Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
203 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
223 reg2 ## __ ## mask2 ## _MASK,\
225 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
A Dirq_service_dcn31.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
219 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
221 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
233 reg2 ## __ ## mask2 ## _MASK,\
235 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
A Dirq_service_dcn21.c241 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
251 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
253 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
255 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
265 reg2 ## __ ## mask2 ## _MASK,\
267 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/net/hamradio/
A Dbaycom_par.c206 unsigned int data, mask, mask2, descx; in par96_rx() local
235 for(mask = 0x1fe00, mask2 = 0xfc00, i = 0; in par96_rx()
236 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) in par96_rx()
237 if ((bc->modem.par96.dcd_shreg & mask) == mask2) in par96_rx()
240 for(mask = 0x1fe00, mask2 = 0x1fe00, i = 0; in par96_rx()
241 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) in par96_rx()
242 if (((bc->modem.par96.dcd_shreg & mask) == mask2) && in par96_rx()
A Dhdlcdrv.c158 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local
176 for(i = 15, mask1 = 0x1fc00, mask2 = 0x1fe00, mask3 = 0x0fc00, in hdlcdrv_receiver()
179 i--, mask1 <<= 1, mask2 <<= 1, mask3 <<= 1, mask4 <<= 1, in hdlcdrv_receiver()
183 else if ((s->hdlcrx.bitstream & mask2) == mask3) { in hdlcdrv_receiver()
254 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local
330 mask2 = 0x10000; in hdlcdrv_transmitter()
333 for(i = 0; i < 8; i++, mask1 <<= 1, mask2 <<= 1, in hdlcdrv_transmitter()
337 s->hdlctx.bitstream &= ~mask2; in hdlcdrv_transmitter()
/linux/arch/alpha/kernel/
A Dsys_titan.c69 unsigned long mask0, mask1, mask2, mask3, dummy; in titan_update_irq_hw() local
75 mask2 = mask & titan_cpu_irq_affinity[2]; in titan_update_irq_hw()
80 else if (bcpu == 2) mask2 |= isa_enable; in titan_update_irq_hw()
94 *dim2 = mask2; in titan_update_irq_hw()
A Dsys_dp264.c55 unsigned long mask0, mask1, mask2, mask3, dummy; in tsunami_update_irq_hw() local
60 mask2 = mask & cpu_irq_affinity[2]; in tsunami_update_irq_hw()
65 else if (bcpu == 2) mask2 |= isa_enable; in tsunami_update_irq_hw()
79 *dim2 = mask2; in tsunami_update_irq_hw()
/linux/fs/affs/
A Dbitmap.c122 u32 blk, bmap, bit, mask, mask2, tmp; in affs_alloc_block() local
208 mask2 = mask = 1 << (bit & 31); in affs_alloc_block()
212 while ((mask2 <<= 1)) { in affs_alloc_block()
213 if (!(tmp & mask2)) in affs_alloc_block()
216 mask |= mask2; in affs_alloc_block()
/linux/drivers/media/test-drivers/vidtv/
A Dvidtv_pes.c89 u64 mask2; in vidtv_pes_write_pts_dts() local
96 mask2 = GENMASK_ULL(29, 15); in vidtv_pes_write_pts_dts()
102 pts_dts.pts2 = cpu_to_be16(((args->pts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()
106 pts_dts.dts2 = cpu_to_be16(((args->dts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()
114 pts.pts2 = cpu_to_be16(((args->pts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()
/linux/drivers/power/supply/
A Drt9455_charger.c854 unsigned int irq1, mask1, mask2; in rt9455_irq_handler_check_irq1_register() local
896 ret = regmap_read(info->regmap, RT9455_REG_MASK2, &mask2); in rt9455_irq_handler_check_irq1_register()
902 if (mask2 & GET_MASK(F_CHTERMIM)) { in rt9455_irq_handler_check_irq1_register()
911 if (mask2 & GET_MASK(F_CHRCHGIM)) { in rt9455_irq_handler_check_irq1_register()
948 unsigned int irq2, mask2; in rt9455_irq_handler_check_irq2_register() local
959 ret = regmap_read(info->regmap, RT9455_REG_MASK2, &mask2); in rt9455_irq_handler_check_irq2_register()
989 if ((mask2 & GET_MASK(F_CHTERMIM)) == 0) { in rt9455_irq_handler_check_irq2_register()
1000 mask2 = mask2 | GET_MASK(F_CHTERMIM); in rt9455_irq_handler_check_irq2_register()
1014 if (mask2 & GET_MASK(F_CHTERMIM)) { in rt9455_irq_handler_check_irq2_register()
1022 mask2 = mask2 & ~GET_MASK(F_CHTERMIM); in rt9455_irq_handler_check_irq2_register()
/linux/include/linux/
A Dcpumask.h184 #define for_each_cpu_and(cpu, mask1, mask2) \ argument
185 for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask1, (void)mask2)
288 #define for_each_cpu_and(cpu, mask1, mask2) \ argument
290 (cpu) = cpumask_next_and((cpu), (mask1), (mask2)), \
604 #define cpumask_any_and(mask1, mask2) cpumask_first_and((mask1), (mask2)) argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/
A Dirq_service_dce120.c105 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
115 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
117 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/
A Dirq_service_dcn303.c110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
118 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
119 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/
A Dirq_service_dcn201.c160 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
170 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
172 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/
A Dirq_service_dcn10.c203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
213 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
215 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

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