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Searched refs:mask_base (Results 1 – 25 of 69) sorted by relevance

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/linux/drivers/mfd/
A Dintel_soc_pmic_bxtwc.c143 .mask_base = BXTWC_MIRQLVL1,
152 .mask_base = BXTWC_MPWRBTNIRQ,
161 .mask_base = BXTWC_MTMUIRQ,
170 .mask_base = BXTWC_MBCUIRQ,
179 .mask_base = BXTWC_MADCIRQ,
188 .mask_base = BXTWC_MCHGR0IRQ,
197 .mask_base = BXTWC_MCRITIRQ,
A Dsec-irq.c381 .mask_base = S2MPS11_REG_INT1M,
390 .mask_base = S2MPS14_REG_INT1M, \
414 .mask_base = S2MPU02_REG_INT1M,
424 .mask_base = S5M8767_REG_INT1M,
434 .mask_base = S5M8763_REG_IRQM1,
A Dmax77693.c68 .mask_base = MAX77693_LED_REG_FLASH_INT_MASK,
84 .mask_base = MAX77693_PMIC_REG_TOPSYS_INT_MASK,
102 .mask_base = MAX77693_CHG_REG_CHG_INT_MASK,
139 .mask_base = MAX77693_MUIC_REG_INTMASK1,
A Dretu-mfd.c80 .mask_base = RETU_REG_IMR,
116 .mask_base = TAHVO_REG_IMR,
265 ret = retu_write(rdev, rdat->irq_chip->mask_base, 0xffff); in retu_probe()
A Dmotorola-cpcap.c98 .mask_base = CPCAP_REG_MIM1,
107 .mask_base = CPCAP_REG_MIM2,
116 .mask_base = CPCAP_REG_INTM1,
A Dmax8907.c132 .mask_base = MAX8907_REG_CHG_IRQ1_MASK,
156 .mask_base = MAX8907_REG_ON_OFF_IRQ1_MASK,
171 .mask_base = MAX8907_REG_RTC_IRQ_MASK,
A Daxp20x.c509 .mask_base = AXP152_IRQ1_EN,
521 .mask_base = AXP20X_IRQ1_EN,
534 .mask_base = AXP20X_IRQ1_EN,
546 .mask_base = AXP20X_IRQ1_EN,
559 .mask_base = AXP20X_IRQ1_EN,
571 .mask_base = AXP20X_IRQ1_EN,
583 .mask_base = AXP20X_IRQ1_EN,
A Dda9063-irq.c94 .mask_base = DA9063_REG_IRQ_MASK_A,
166 .mask_base = DA9063_REG_IRQ_MASK_A,
A Dmax14577.c212 .mask_base = MAX14577_REG_INTMASK1,
242 .mask_base = MAX14577_REG_INTMASK1,
257 .mask_base = MAX77836_PMIC_REG_TOPSYS_INT_MASK,
A Drk808.c488 .mask_base = RK805_INT_STS_MSK_REG,
500 .mask_base = RK808_INT_STS_MSK_REG1,
512 .mask_base = RK817_INT_STS_MSK_REG0,
524 .mask_base = RK818_INT_STS_MSK_REG1,
A Dmax77686.c133 .mask_base = MAX77686_REG_INT1MSK,
142 .mask_base = MAX77802_REG_INT1MSK,
A Dbd9571mwv.c99 .mask_base = BD9571MWV_INT_INTMASK,
165 .mask_base = BD9571MWV_INT_INTMASK,
A Datc260x-core.c103 .mask_base = ATC2603C_INTS_MSK,
113 .mask_base = ATC2609A_INTS_MSK,
A Dintel_soc_pmic_crc.c123 .mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
A Dtps65910.c207 .mask_base = TPS65910_INT_MSK,
218 .mask_base = TPS65910_INT_MSK,
A Drt5033.c32 .mask_base = RT5033_REG_PMIC_IRQ_CTRL,
A Dtps65912-core.c74 .mask_base = TPS65912_INT_MSK,
A Dtps65086.c58 .mask_base = TPS65086_IRQ_MASK,
A Drohm-bd9576.c84 .mask_base = BD957X_REG_INT_MAIN_MASK,
A Dintel_soc_pmic_chtdc_ti.c103 .mask_base = CHTDC_TI_MASK_IRQLVL1,
A Dsun4i-gpadc.c37 .mask_base = SUN4I_GPADC_INT_FIFOC,
A Dtps65090.c130 .mask_base = TPS65090_REG_INTR_MASK,
/linux/drivers/base/regmap/
A Dregmap-irq.c129 if (!d->chip->mask_base) in regmap_irq_sync_unlock()
132 reg = sub_irq_reg(d, d->chip->mask_base, i); in regmap_irq_sync_unlock()
145 d->chip->mask_base; in regmap_irq_sync_unlock()
771 if (!chip->mask_base) in regmap_add_irq_chip_fwnode()
774 reg = sub_irq_reg(d, d->chip->mask_base, i); in regmap_add_irq_chip_fwnode()
781 d->chip->mask_base; in regmap_add_irq_chip_fwnode()
/linux/drivers/irqchip/
A Dirq-sl28cpld.c68 irqchip->chip.mask_base = base + INTC_IE; in sl28cpld_intc_probe()
/linux/drivers/gpio/
A Dgpio-sl28cpld.c73 irq_chip->mask_base = base + GPIO_REG_IE; in sl28cpld_gpio_irq_init()

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