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Searched refs:masks (Results 1 – 25 of 227) sorted by relevance

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/linux/drivers/clk/mmp/
A Dclk-frac.c57 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_recalc_rate() local
64 num = (val >> masks->num_shift) & masks->num_mask; in clk_factor_recalc_rate()
67 den = (val >> masks->den_shift) & masks->den_mask; in clk_factor_recalc_rate()
84 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_set_rate() local
106 val &= ~(masks->num_mask << masks->num_shift); in clk_factor_set_rate()
109 val &= ~(masks->den_mask << masks->den_shift); in clk_factor_set_rate()
134 num = (val >> masks->num_shift) & masks->num_mask; in clk_factor_init()
137 den = (val >> masks->den_shift) & masks->den_mask; in clk_factor_init()
144 val &= ~(masks->num_mask << masks->num_shift); in clk_factor_init()
148 val &= ~(masks->den_mask << masks->den_shift); in clk_factor_init()
[all …]
/linux/drivers/clk/spear/
A Dclk-aux-synth.c80 eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask; in clk_aux_recalc_rate()
86 aux->masks->xscale_sel_mask; in clk_aux_recalc_rate()
90 aux->masks->yscale_sel_mask; in clk_aux_recalc_rate()
114 ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift); in clk_aux_set_rate()
116 aux->masks->eq_sel_shift; in clk_aux_set_rate()
117 val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift); in clk_aux_set_rate()
119 aux->masks->xscale_sel_shift; in clk_aux_set_rate()
120 val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift); in clk_aux_set_rate()
122 aux->masks->yscale_sel_shift; in clk_aux_set_rate()
156 if (!masks) in clk_register_aux()
[all …]
/linux/kernel/irq/
A Daffinity.c45 cpumask_var_t *masks; in alloc_node_to_cpumask() local
49 if (!masks) in alloc_node_to_cpumask()
57 return masks; in alloc_node_to_cpumask()
62 kfree(masks); in alloc_node_to_cpumask()
72 kfree(masks); in free_node_to_cpumask()
272 cpumask_or(&masks[curvec].mask, &masks[curvec].mask, in __irq_build_affinity_masks()
382 masks); in irq_build_affinity_masks()
449 masks = kcalloc(nvecs, sizeof(*masks), GFP_KERNEL); in irq_create_affinity_masks()
450 if (!masks) in irq_create_affinity_masks()
468 kfree(masks); in irq_create_affinity_masks()
[all …]
/linux/drivers/net/dsa/microchip/
A Dksz8795.c278 const u32 *masks; in ksz8_r_mib_cnt() local
285 masks = ksz8->masks; in ksz8_r_mib_cnt()
322 masks = ksz8->masks; in ksz8795_r_mib_pkt()
489 masks = ksz8->masks; in ksz8_valid_dyn_entry()
525 masks = ksz8->masks; in ksz8_r_dyn_mac_table()
586 masks = ksz8->masks; in ksz8_r_sta_mac_table()
625 masks = ksz8->masks; in ksz8_w_sta_mac_table()
656 masks = ksz8->masks; in ksz8_from_vlan()
672 masks = ksz8->masks; in ksz8_to_vlan()
1313 masks = ksz8->masks; in ksz8_port_setup()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_dpp_cm.c119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
214 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
216 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
270 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
274 reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; in dpp1_cm_get_reg_field()
278 reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_reg_field()
297 reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_degamma_reg_field()
305 reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_degamma_reg_field()
470 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp1_program_input_csc()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_i2c_hw.c86 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE) in get_channel_status()
624 const struct dce_i2c_mask *masks) in dce_i2c_hw_construct() argument
631 dce_i2c_hw->masks = masks; in dce_i2c_hw_construct()
647 const struct dce_i2c_mask *masks) in dce100_i2c_hw_construct() argument
654 masks); in dce100_i2c_hw_construct()
664 const struct dce_i2c_mask *masks) in dce112_i2c_hw_construct() argument
671 masks); in dce112_i2c_hw_construct()
681 const struct dce_i2c_mask *masks) in dcn1_i2c_hw_construct() argument
688 masks); in dcn1_i2c_hw_construct()
698 const struct dce_i2c_mask *masks) in dcn2_i2c_hw_construct() argument
[all …]
A Ddce_i2c_hw.h292 const struct dce_i2c_mask *masks; member
301 const struct dce_i2c_mask *masks);
309 const struct dce_i2c_mask *masks);
317 const struct dce_i2c_mask *masks);
325 const struct dce_i2c_mask *masks);
333 const struct dce_i2c_mask *masks);
/linux/arch/riscv/mm/
A Dpageattr.c19 struct pageattr_masks *masks = walk->private; in set_pageattr_masks() local
22 new_val &= ~(pgprot_val(masks->clear_mask)); in set_pageattr_masks()
23 new_val |= (pgprot_val(masks->set_mask)); in set_pageattr_masks()
113 struct pageattr_masks masks = { in __set_memory() local
123 &masks); in __set_memory()
164 struct pageattr_masks masks = { in set_direct_map_invalid_noflush() local
170 ret = walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); in set_direct_map_invalid_noflush()
181 struct pageattr_masks masks = { in set_direct_map_default_noflush() local
187 ret = walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); in set_direct_map_default_noflush()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_dwb_cm.c53 reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
55 reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
58 reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
60 reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
62 reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam()
67 reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam()
69 reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam()
71 reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B; in dwb3_get_reg_field_ogam()
75 reg->masks.exp_region_start = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_B; in dwb3_get_reg_field_ogam()
316 gam_regs.masks.csc_c11 = dwbc30->dwbc_mask->DWB_GAMUT_REMAPA_C11; in dwb3_program_gamut_remap()
[all …]
A Ddcn30_dpp_cm.c180 reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
182 reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
185 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
187 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
189 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
194 reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
196 reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
198 reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
202 reg->masks.exp_region_start = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_B; in dpp3_gamcor_reg_field()
348 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
[all …]
A Ddcn30_mpc.c182 reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
185 reg->masks.exp_region0_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc3_ogam_get_reg_field()
194 reg->masks.field_region_end = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc3_ogam_get_reg_field()
198 reg->masks.field_region_end_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc3_ogam_get_reg_field()
202 reg->masks.exp_region_start = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B; in mpc3_ogam_get_reg_field()
1084 gam_regs.masks.csc_c11 = mpc30->mpc_mask->MPCC_GAMUT_REMAP_C11_A; in program_gamut_remap()
1086 gam_regs.masks.csc_c12 = mpc30->mpc_mask->MPCC_GAMUT_REMAP_C12_A; in program_gamut_remap()
1256 ocsc_regs.masks.csc_c11 = mpc30->mpc_mask->MPC_OCSC_C11_A; in mpc3_set_output_csc()
1258 ocsc_regs.masks.csc_c12 = mpc30->mpc_mask->MPC_OCSC_C12_A; in mpc3_set_output_csc()
1298 ocsc_regs.masks.csc_c11 = mpc30->mpc_mask->MPC_OCSC_C11_A; in mpc3_set_ocsc_default()
[all …]
/linux/drivers/clk/uniphier/
A Dclk-uniphier-mux.c17 const unsigned int *masks; member
27 return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index], in uniphier_clk_mux_set_parent()
44 if ((mux->masks[i] & val) == mux->vals[i]) in uniphier_clk_mux_get_parent()
77 mux->masks = data->masks; in uniphier_clk_register_mux()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_mpc.c165 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc()
167 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc()
223 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
225 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
251 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
253 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
255 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field()
259 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
261 reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc2_ogam_get_reg_field()
263 reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc2_ogam_get_reg_field()
[all …]
A Ddcn20_dpp_cm.c190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
192 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
285 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp2_program_input_csc()
287 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; in dpp2_program_input_csc()
363 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
365 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
367 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
372 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
374 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
376 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field()
[all …]
/linux/drivers/s390/char/
A Dsclp.h97 u8 masks[4 * 1021]; /* variable length */ member
108 static inline sccb_mask_t sccb_get_mask(u8 *masks, size_t len, int i) in sccb_get_mask() argument
112 memcpy(&res, masks + i * len, min(sizeof(res), len)); in sccb_get_mask()
116 static inline void sccb_set_mask(u8 *masks, size_t len, int i, sccb_mask_t val) in sccb_set_mask() argument
118 memset(masks + i * len, 0, len); in sccb_set_mask()
119 memcpy(masks + i * len, &val, min(sizeof(val), len)); in sccb_set_mask()
126 sccb_get_mask(__sccb->masks, __sccb->mask_length, i); \
137 sccb_set_mask(__sccb->masks, __sccb->mask_length, i, val); \
/linux/Documentation/devicetree/bindings/usb/
A Dbrcm,usb-pinmap.yaml33 brcm,in-masks:
45 brcm,out-masks:
47 description: Array of enable, value, changed and clear masks, one
66 brcm,in-masks = <0x8000 0x40000 0x10000 0x80000>;
69 brcm,out-masks = <0x20000 0x800000 0x400000 0x200000>;
/linux/drivers/net/ethernet/intel/ice/
A Dice_flex_pipe.c2697 if (hw->blk[blk].masks.masks[i].in_use && in ice_prof_has_mask_idx()
3003 memset(hw->blk[blk].masks.masks, 0, sizeof(hw->blk[blk].masks.masks)); in ice_init_prof_masks()
3044 if (hw->blk[blk].masks.masks[i].in_use) { in ice_alloc_prof_mask()
3074 hw->blk[blk].masks.masks[i].mask = mask; in ice_alloc_prof_mask()
3075 hw->blk[blk].masks.masks[i].idx = idx; in ice_alloc_prof_mask()
3076 hw->blk[blk].masks.masks[i].ref = 0; in ice_alloc_prof_mask()
3080 hw->blk[blk].masks.masks[i].ref++; in ice_alloc_prof_mask()
3112 hw->blk[blk].masks.masks[mask_idx].ref--; in ice_free_prof_mask()
3173 hw->blk[blk].masks.masks[i].idx = 0; in ice_shutdown_prof_masks()
3174 hw->blk[blk].masks.masks[i].mask = 0; in ice_shutdown_prof_masks()
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/linux/Documentation/devicetree/bindings/sound/
A Dtdm-slot.txt20 tx and rx masks.
22 For snd_soc_of_xlate_tdm_slot_mask(), the tx and rx masks will use a 1 bit
24 the masks.
26 The explicit masks are given as array of integers, where the first
/linux/net/openvswitch/
A Dflow_table.c261 if (ovsl_dereference(old->masks[i])) in tbl_mask_array_realloc()
262 new->masks[new->count++] = old->masks[i]; in tbl_mask_array_realloc()
294 rcu_assign_pointer(ma->masks[ma_count], new); in tbl_mask_array_add_mask()
308 if (mask == ovsl_dereference(ma->masks[i])) in tbl_mask_array_del_mask()
318 rcu_assign_pointer(ma->masks[i], ma->masks[ma_count - 1]); in tbl_mask_array_del_mask()
761 mask = rcu_dereference_ovsl(ma->masks[i]); in flow_lookup()
882 mask = ovsl_dereference(ma->masks[i]); in ovs_flow_tbl_lookup_exact()
998 t = ovsl_dereference(ma->masks[i]); in flow_mask_find()
1125 mask = rcu_dereference_ovsl(ma->masks[i]); in ovs_flow_masks_rebalance()
1180 if (ovsl_dereference(ma->masks[index])) in ovs_flow_masks_rebalance()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_hubbub.c38 hubbub1->shifts->field_name, hubbub1->masks->field_name
48 hubbub1->shifts->field_name, hubbub1->masks->field_name
78 hubbub3->masks = hubbub_mask; in hubbub301_construct()
/linux/drivers/gpu/drm/via/
A Dvia_irq.c211 maskarray_t *masks; in via_driver_irq_wait() local
234 masks = dev_priv->irq_masks; in via_driver_irq_wait()
237 if (masks[real_irq][2] && !force_sequence) { in via_driver_irq_wait()
239 ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) == in via_driver_irq_wait()
240 masks[irq][4])); in via_driver_irq_wait()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_hubbub.c41 hubbub1->shifts->field_name, hubbub1->masks->field_name
51 hubbub1->shifts->field_name, hubbub1->masks->field_name
103 hubbub->masks = hubbub_mask; in hubbub201_construct()
/linux/tools/perf/trace/beauty/
A Dprctl.c65 const u8 masks[] = { in syscall_arg__scnprintf_prctl_option() local
78 if (option < ARRAY_SIZE(masks)) in syscall_arg__scnprintf_prctl_option()
79 arg->mask |= masks[option]; in syscall_arg__scnprintf_prctl_option()
/linux/Documentation/devicetree/bindings/mux/
A Dreg-mux.yaml27 mux-reg-masks:
35 - mux-reg-masks
49 mux-reg-masks =
106 mux-reg-masks =
/linux/drivers/edac/
A Ddmc520_edac.c173 int masks[NUMBER_OF_IRQS]; member
436 mask = pvt->masks[idx]; in dmc520_isr()
477 int masks[NUMBER_OF_IRQS] = { 0 }; in dmc520_edac_probe() local
494 masks[idx] = dmc520_irq_configs[idx].mask; in dmc520_edac_probe()
533 memcpy(pvt->masks, masks, sizeof(masks)); in dmc520_edac_probe()
622 irq_mask_all |= pvt->masks[idx]; in dmc520_edac_remove()

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