Searched refs:mast (Results 1 – 4 of 4) sorted by relevance
133 src = !!(mast & 0x00200000); in read_pll_ref()136 src = !!(mast & 0x00400000); in read_pll_ref()139 src = !!(mast & 0x00010000); in read_pll_ref()142 src = !!(mast & 0x02000000); in read_pll_ref()212 switch (mast & 0x30000000) { in nv50_clk_read()220 if (!(mast & 0x00100000)) in nv50_clk_read()222 switch (mast & 0x00000003) { in nv50_clk_read()231 switch (mast & 0x00000030) { in nv50_clk_read()233 if (mast & 0x00000080) in nv50_clk_read()244 switch (mast & 0x0000c000) { in nv50_clk_read()[all …]
99 switch (mast & 0x000c0000) { in mcp77_clk_read()109 switch (mast & 0x00000003) { in mcp77_clk_read()133 if (mast & 0x00000040) in mcp77_clk_read()301 u32 pllmask = 0, mast; in mcp77_clk_prog() local312 mast &= ~0x00400e73; in mcp77_clk_prog()313 mast |= 0x03000000; in mcp77_clk_prog()318 mast |= 0x00000002; in mcp77_clk_prog()325 mast |= 0x00000003; in mcp77_clk_prog()339 mast |= 0x00000020; in mcp77_clk_prog()346 mast |= 0x00000030; in mcp77_clk_prog()[all …]
102 u32 mast = nvkm_rd32(device, 0x00c040); in nv40_clk_read() local110 return read_clk(clk, (mast & 0x00000003) >> 0); in nv40_clk_read()112 return read_clk(clk, (mast & 0x00000030) >> 4); in nv40_clk_read()119 nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast); in nv40_clk_read()
47 even. The tuples mast be ordered (low, high) and are
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