| /linux/tools/testing/selftests/drivers/net/mlxsw/ |
| A D | ethtool_lanes.sh | 55 local max_lanes=$1; shift
59 local unsupported_lanes=$((max_lanes *= 2))
73 local max_lanes
110 local max_lanes
115 max_lanes=${max_values[1]}
117 lanes=$max_lanes
134 check_unsupported_lanes $swp1 $max_speed $max_lanes 1
147 local max_lanes
152 max_lanes=${max_values[1]}
154 lanes=$max_lanes
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| /linux/tools/testing/selftests/net/ |
| A D | devlink_port_split.py | 156 max_lanes = get_max_lanes(port)
160 if max_lanes != lanes:
162 % (port, lanes, max_lanes))
259 max_lanes = get_max_lanes(port.name)
262 if max_lanes == 0:
266 elif max_lanes == 1:
269 split_unsplittable_port(port, max_lanes)
273 lane = max_lanes
277 split_splittable_port(port, lane, max_lanes, dev)
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| /linux/drivers/media/platform/cadence/ |
| A D | cdns-csi2rx.c | 75 u8 max_lanes; member
129 for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) { in csi2rx_start()
131 csi2rx->max_lanes); in csi2rx_start()
326 csi2rx->max_lanes = dev_cfg & 7; in csi2rx_get_resources()
327 if (csi2rx->max_lanes > CSI2RX_LANES_MAX) { in csi2rx_get_resources()
329 csi2rx->max_lanes); in csi2rx_get_resources()
395 if (csi2rx->num_lanes > csi2rx->max_lanes) { in csi2rx_parse_dt()
464 csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, in csi2rx_probe()
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| A D | cdns-csi2tx.c | 116 unsigned int max_lanes; member
465 csi2tx->max_lanes = dev_cfg & CSI2TX_DEVICE_CONFIG_LANES_MASK; in csi2tx_get_resources()
466 if (csi2tx->max_lanes > CSI2TX_LANES_MAX) { in csi2tx_get_resources()
468 csi2tx->max_lanes); in csi2tx_get_resources()
520 if (csi2tx->num_lanes > csi2tx->max_lanes) { in csi2tx_check_lanes()
627 csi2tx->num_lanes, csi2tx->max_lanes, csi2tx->max_streams, in csi2tx_probe()
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| /linux/drivers/gpu/drm/xlnx/ |
| A D | zynqmp_dp.c | 248 u8 max_lanes; member
565 u8 max_lanes = dp->link_config.max_lanes; in zynqmp_dp_mode_configure() local
587 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) { in zynqmp_dp_mode_configure()
1316 link_config->max_lanes = min_t(u8, in zynqmp_dp_connector_detect()
1358 u8 max_lanes = dp->link_config.max_lanes; in zynqmp_dp_connector_mode_valid() local
1371 rate = zynqmp_dp_max_rate(max_rate, max_lanes, bpp); in zynqmp_dp_connector_mode_valid()
1457 u8 max_lanes = dp->link_config.max_lanes; in zynqmp_dp_encoder_atomic_mode_set() local
1465 rate = zynqmp_dp_max_rate(max_rate, max_lanes, bpp); in zynqmp_dp_encoder_atomic_mode_set()
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| /linux/drivers/gpu/drm/rockchip/ |
| A D | cdn-dp-reg.c | 539 dp->max_lanes = status[1]; in cdn_dp_get_training_status()
564 dp->max_lanes); in cdn_dp_train_link()
662 do_div(symbol, dp->max_lanes * link_rate * 8); in cdn_dp_config_video()
668 mode->clock, dp->max_lanes, link_rate); in cdn_dp_config_video()
682 val /= (dp->max_lanes * link_rate); in cdn_dp_config_video()
835 if (dp->max_lanes == 1) in cdn_dp_audio_config_i2s()
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| A D | cdn-dp-core.h | 97 u8 max_lanes; member
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| A D | cdn-dp-core.c | 483 dp->max_lanes = 0; in cdn_dp_disable()
576 if (!port || !dp->max_rate || !dp->max_lanes) in cdn_dp_check_link_status()
954 unsigned int lanes = dp->max_lanes; in cdn_dp_pd_event_work()
967 (rate != dp->max_rate || lanes != dp->max_lanes)) { in cdn_dp_pd_event_work()
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| /linux/drivers/gpu/drm/tegra/ |
| A D | dp.c | 43 link->max_lanes = 0; in drm_dp_link_reset()
184 link->max_lanes = drm_dp_max_lane_count(dpcd); in drm_dp_link_probe()
233 link->lanes = link->max_lanes; in drm_dp_link_probe()
402 for (i = 0; i < ARRAY_SIZE(lanes) && lanes[i] <= link->max_lanes; i++) { in drm_dp_link_choose()
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| A D | dp.h | 125 unsigned int max_lanes; member
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| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_tc.c | 482 int max_lanes; in icl_tc_phy_connect() local
501 max_lanes = intel_tc_port_fia_max_lane_count(dig_port); in icl_tc_phy_connect()
503 drm_WARN_ON(&i915->drm, max_lanes != 4); in icl_tc_phy_connect()
519 if (max_lanes < required_lanes) { in icl_tc_phy_connect()
523 max_lanes, required_lanes); in icl_tc_phy_connect()
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| A D | intel_dp_mst.c | 698 int max_rate, mode_rate, max_lanes, max_link_clock; in intel_dp_mst_mode_valid_ctx() local
712 max_lanes = intel_dp_max_lane_count(intel_dp); in intel_dp_mst_mode_valid_ctx()
714 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); in intel_dp_mst_mode_valid_ctx()
977 dig_port->max_lanes, in intel_dp_mst_encoder_init()
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| A D | intel_dp.h | 81 int intel_dp_max_data_rate(int max_link_rate, int max_lanes);
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| A D | intel_dp.c | 233 int source_max = dig_port->max_lanes; in intel_dp_max_common_lane_count()
281 intel_dp_max_data_rate(int max_link_rate, int max_lanes) in intel_dp_max_data_rate() argument
305 return max_link_rate * max_lanes; in intel_dp_max_data_rate()
858 int max_rate, mode_rate, max_lanes, max_link_clock; in intel_dp_mode_valid() local
890 max_lanes = intel_dp_max_lane_count(intel_dp); in intel_dp_mode_valid()
921 max_lanes, in intel_dp_mode_valid()
2140 int max_lanes, rate_per_lane; in intel_dp_hdmi_sink_max_frl() local
2143 max_lanes = connector->display_info.hdmi.max_lanes; in intel_dp_hdmi_sink_max_frl()
2145 max_frl_rate = max_lanes * rate_per_lane; in intel_dp_hdmi_sink_max_frl()
4994 if (drm_WARN(dev, dig_port->max_lanes < 1, in intel_dp_init_connector()
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| A D | intel_ddi.c | 993 if (encoder->port == PORT_A && dig_port->max_lanes == 4) in skl_ddi_set_iboost()
4227 int max_lanes = 4; in intel_ddi_max_lanes() local
4230 return max_lanes; in intel_ddi_max_lanes()
4234 max_lanes = port == PORT_A ? 4 : 0; in intel_ddi_max_lanes()
4237 max_lanes = 2; in intel_ddi_max_lanes()
4249 max_lanes = 4; in intel_ddi_max_lanes()
4252 return max_lanes; in intel_ddi_max_lanes()
4600 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); in intel_ddi_init()
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| A D | g4x_hdmi.c | 612 dig_port->max_lanes = 4; in g4x_hdmi_init()
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| A D | intel_display_types.h | 1668 u8 max_lanes; member
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| A D | g4x_dp.c | 1385 dig_port->max_lanes = 4; in g4x_dp_init()
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| A D | intel_hdmi.c | 2867 if (drm_WARN(dev, dig_port->max_lanes < 4, in intel_hdmi_init_connector()
2869 dig_port->max_lanes, intel_encoder->base.base.id, in intel_hdmi_init_connector()
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| /linux/include/drm/ |
| A D | drm_connector.h | 210 u8 max_lanes; member
255 u8 max_lanes; member
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| /linux/drivers/gpu/drm/gma500/ |
| A D | cdv_intel_dp.c | 375 cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes) in cdv_intel_dp_max_data_rate() argument
377 return (max_link_clock * max_lanes * 19) / 20; in cdv_intel_dp_max_data_rate()
517 int max_lanes = cdv_intel_dp_max_lane_count(encoder); in cdv_intel_dp_mode_valid() local
531 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes))) in cdv_intel_dp_mode_valid()
536 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)) in cdv_intel_dp_mode_valid()
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| /linux/drivers/gpu/drm/ |
| A D | drm_edid.c | 4906 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) in drm_get_max_frl_rate() argument
4910 *max_lanes = 3; in drm_get_max_frl_rate()
4914 *max_lanes = 3; in drm_get_max_frl_rate()
4918 *max_lanes = 4; in drm_get_max_frl_rate()
4922 *max_lanes = 4; in drm_get_max_frl_rate()
4926 *max_lanes = 4; in drm_get_max_frl_rate()
4930 *max_lanes = 4; in drm_get_max_frl_rate()
4935 *max_lanes = 0; in drm_get_max_frl_rate()
5001 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, in drm_parse_hdmi_forum_vsdb()
5019 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, in drm_parse_hdmi_forum_vsdb()
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| A D | drm_dp_helper.c | 2311 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER); in drm_dp_lttpr_max_lane_count() local
2313 return max_lanes & DP_MAX_LANE_COUNT_MASK; in drm_dp_lttpr_max_lane_count()
2902 for (i = 0; i < hdmi->max_lanes; i++) { in drm_dp_pcon_hdmi_frl_link_error_count()
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| /linux/drivers/gpu/drm/bridge/analogix/ |
| A D | analogix_dp_core.c | 641 u32 max_lanes, u32 max_rate) in analogix_dp_full_link_train() argument
671 if (dp->link_train.lane_count > max_lanes) in analogix_dp_full_link_train()
672 dp->link_train.lane_count = max_lanes; in analogix_dp_full_link_train()
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