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Searched refs:mc_writel (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/memory/tegra/
A Dtegra20.c287 mc_writel(mc, value & ~BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_assert()
303 mc_writel(mc, value | BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_deassert()
319 mc_writel(mc, value, rst->control); in tegra20_mc_block_dma()
347 mc_writel(mc, value, rst->control); in tegra20_mc_unblock_dma()
460 mc_writel(mc, 0x00000000, MC_STAT_CONTROL); in tegra20_mc_stat_gather()
461 mc_writel(mc, control_0, MC_STAT_EMC_CONTROL_0); in tegra20_mc_stat_gather()
462 mc_writel(mc, control_1, MC_STAT_EMC_CONTROL_1); in tegra20_mc_stat_gather()
463 mc_writel(mc, 0xffffffff, MC_STAT_EMC_CLOCK_LIMIT); in tegra20_mc_stat_gather()
465 mc_writel(mc, EMC_GATHER_ENABLE, MC_STAT_CONTROL); in tegra20_mc_stat_gather()
467 mc_writel(mc, EMC_GATHER_DISABLE, MC_STAT_CONTROL); in tegra20_mc_stat_gather()
[all …]
A Dmc.c116 mc_writel(mc, value, rst->control); in tegra_mc_block_dma_common()
138 mc_writel(mc, value, rst->control); in tegra_mc_unblock_dma_common()
334 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); in tegra_mc_write_emem_configuration()
370 mc_writel(mc, value, MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
380 mc_writel(mc, value, client->regs.la.reg); in tegra_mc_setup_latency_allowance()
384 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in tegra_mc_setup_latency_allowance()
491 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); in tegra30_mc_probe()
600 mc_writel(mc, status, MC_INTSTATUS); in tegra30_mc_handle_irq()
764 mc_writel(mc, mc->soc->intmask, MC_INTMASK); in tegra_mc_probe()
A Dmc.h100 static inline void mc_writel(const struct tegra_mc *mc, u32 value, in mc_writel() function
A Dtegra30-emc.c576 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
577 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in emc_prepare_timing_change()
581 mc_writel(emc->mc, in emc_prepare_timing_change()
823 mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE); in emc_complete_timing_change()
A Dtegra210-emc-cc-r21021.c1216 mc_writel(emc->mc, values[i], offsets[i]); in tegra210_emc_r21021_set_clock()
1228 mc_writel(emc->mc, next->la_scale_regs[i], la[i]); in tegra210_emc_r21021_set_clock()
1666 mc_writel(emc->mc, next->la_scale_regs[i], in tegra210_emc_r21021_set_clock()
A Dtegra30.c1288 mc_writel(mc, value, client->regs.la.reg); in tegra30_mc_tune_client_latency()

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