Searched refs:mem_table (Results 1 – 15 of 15) sorted by relevance
306 struct pdc_pat_pd_addr_map_entry mem_table[PAT_MAX_RANGES+1]; in pat_memconfig() local316 status = pdc_pat_pd_get_addr_map(&actual_len, mem_table, length, 0L); in pat_memconfig()345 mtbl_ptr = mem_table; in pat_memconfig()400 struct pdc_memory_table mem_table[MAX_PHYSMEM_RANGES]; in sprockets_memconfig() local407 status = pdc_mem_mem_table(&r_addr,mem_table, in sprockets_memconfig()430 mtbl_ptr = mem_table; in sprockets_memconfig()
671 dpm_table = &(data->dpm_table.mem_table); in vega12_setup_default_dpm_tables()1638 data->dpm_table.mem_table.dpm_state.soft_min_level = in vega12_force_dpm_highest()1639 data->dpm_table.mem_table.dpm_state.soft_max_level = in vega12_force_dpm_highest()1667 data->dpm_table.mem_table.dpm_state.soft_min_level = in vega12_force_dpm_lowest()1668 data->dpm_table.mem_table.dpm_state.soft_max_level = in vega12_force_dpm_lowest()1867 dpm_table = &(data->dpm_table.mem_table); in vega12_get_memclocks()2365 dpm_table = &(data->dpm_table.mem_table); in vega12_apply_clocks_adjust_rules()2523 &data->dpm_table.mem_table); in vega12_pre_display_configuration_changed_task()2650 for (i = 0; i < dpm_table->mem_table.count; i++) {2651 if (dpm_table->mem_table.dpm_levels[i].enabled &&[all …]
611 dpm_table = &(data->dpm_table.mem_table); in vega20_setup_memclk_dpm_table()663 dpm_table = &(data->dpm_table.mem_table); in vega20_setup_default_dpm_tables()1068 data->dpm_table.mem_table.dpm_levels[data->dpm_table.mem_table.count - 2].value; in vega20_od8_set_feature_capabilities()1517 &(data->dpm_table.mem_table); in vega20_get_mclk_od()1519 &(data->golden_dpm_table.mem_table); in vega20_get_mclk_od()1536 &(data->golden_dpm_table.mem_table); in vega20_set_mclk_od()1563 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table); in vega20_populate_umdpstate_clocks() local2341 &data->dpm_table.mem_table; in vega20_notify_smc_display_config_after_ps_adjustment()2596 data->dpm_table.mem_table.count - 1); in vega20_force_clock_level()3632 &data->dpm_table.mem_table); in vega20_pre_display_configuration_changed_task()[all …]
1361 data->dpm_table.mem_table.count = 0; in vega10_setup_default_dpm_tables()1362 dpm_table = &(data->dpm_table.mem_table); in vega10_setup_default_dpm_tables()1876 &(data->dpm_table.mem_table); in vega10_populate_all_memory_levels()3537 &(data->dpm_table.mem_table), in vega10_trim_dpm_states()3628 data->dpm_table.mem_table.dpm_state.soft_min_level = in vega10_upload_dpm_bootup_level()3910 if (mclk_idx < dpm_table->mem_table.count) { in vega10_read_sensor()4986 &(data->golden_dpm_table.mem_table); in vega10_get_mclk_od()5001 &(data->golden_dpm_table.mem_table); in vega10_set_mclk_od()5216 golden_table = &(data->golden_dpm_table.mem_table); in vega10_check_clk_voltage_valid()5241 &data->dpm_table.mem_table; in vega10_odn_update_power_state()[all …]
149 struct vega10_single_dpm_table mem_table; member
128 struct vega12_single_dpm_table mem_table; member
180 struct vega20_single_dpm_table mem_table; member
62 struct arcturus_single_dpm_table mem_table; member
1886 struct smu_11_0_dpm_table *mem_table = in smu_v11_0_set_performance_level() local1901 mclk_min = mclk_max = mem_table->max; in smu_v11_0_set_performance_level()1906 mclk_min = mclk_max = mem_table->min; in smu_v11_0_set_performance_level()1912 mclk_min = mem_table->min; in smu_v11_0_set_performance_level()1913 mclk_max = mem_table->max; in smu_v11_0_set_performance_level()
547 struct smu_11_0_dpm_table *mem_table = in arcturus_populate_umd_state_clk() local557 pstate_table->uclk_pstate.min = mem_table->min; in arcturus_populate_umd_state_clk()558 pstate_table->uclk_pstate.peak = mem_table->max; in arcturus_populate_umd_state_clk()564 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL && in arcturus_populate_umd_state_clk()569 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value; in arcturus_populate_umd_state_clk()
1505 struct smu_11_0_dpm_table *mem_table = in navi10_populate_umd_state_clk() local1563 pstate_table->uclk_pstate.min = mem_table->min; in navi10_populate_umd_state_clk()1564 pstate_table->uclk_pstate.peak = mem_table->max; in navi10_populate_umd_state_clk()1570 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && in navi10_populate_umd_state_clk()
1228 struct smu_11_0_dpm_table *mem_table = in sienna_cichlid_populate_umd_state_clk() local1240 pstate_table->uclk_pstate.min = mem_table->min; in sienna_cichlid_populate_umd_state_clk()1241 pstate_table->uclk_pstate.peak = mem_table->max; in sienna_cichlid_populate_umd_state_clk()1242 if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK) in sienna_cichlid_populate_umd_state_clk()
62 struct aldebaran_single_dpm_table mem_table; member
495 struct smu_13_0_dpm_table *mem_table = in aldebaran_populate_umd_state_clk() local507 pstate_table->uclk_pstate.min = mem_table->min; in aldebaran_populate_umd_state_clk()508 pstate_table->uclk_pstate.peak = mem_table->max; in aldebaran_populate_umd_state_clk()509 pstate_table->uclk_pstate.curr.min = mem_table->min; in aldebaran_populate_umd_state_clk()510 pstate_table->uclk_pstate.curr.max = mem_table->max; in aldebaran_populate_umd_state_clk()518 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && in aldebaran_populate_umd_state_clk()523 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; in aldebaran_populate_umd_state_clk()
1638 struct smu_13_0_dpm_table *mem_table = in smu_v13_0_set_performance_level() local1653 mclk_min = mclk_max = mem_table->max; in smu_v13_0_set_performance_level()1658 mclk_min = mclk_max = mem_table->min; in smu_v13_0_set_performance_level()1664 mclk_min = mem_table->min; in smu_v13_0_set_performance_level()1665 mclk_max = mem_table->max; in smu_v13_0_set_performance_level()
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