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Searched refs:mfdcr (Results 1 – 10 of 10) sorted by relevance

/linux/arch/powerpc/platforms/44x/
A Dfsp2.c152 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCSTAT)); in mcue_handler()
160 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR0)); in mcue_handler()
162 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR1)); in mcue_handler()
164 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR2)); in mcue_handler()
166 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR3)); in mcue_handler()
178 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER0)); in mcue_handler()
180 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER1)); in mcue_handler()
182 mfdcr(DCRN_PLB6MCIF_BESR0)); in mcue_handler()
184 mfdcr(DCRN_PLB6MCIF_BEARL)); in mcue_handler()
186 mfdcr(DCRN_PLB6MCIF_BEARH)); in mcue_handler()
[all …]
A Dfsp2.h256 data = mfdcr(DCRN_CMU_DATA); \
268 data = mfdcr(DCRN_L2CDCRDI); \
/linux/arch/powerpc/platforms/4xx/
A Dsoc.c36 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in l2c_diag()
39 return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA); in l2c_diag()
44 u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR); in l2c_error_handler()
126 mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); in ppc4xx_l2c_probe()
128 mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
130 mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
137 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) & in ppc4xx_l2c_probe()
146 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in ppc4xx_l2c_probe()
153 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) & in ppc4xx_l2c_probe()
158 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) & in ppc4xx_l2c_probe()
[all …]
A Duic.c62 er = mfdcr(uic->dcrbase + UIC_ER); in uic_unmask_irq()
76 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_irq()
102 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_ack_irq()
150 tr = mfdcr(uic->dcrbase + UIC_TR); in uic_set_irq_type()
151 pr = mfdcr(uic->dcrbase + UIC_PR); in uic_set_irq_type()
209 msr = mfdcr(uic->dcrbase + UIC_MSR); in uic_irq_cascade()
325 msr = mfdcr(primary_uic->dcrbase + UIC_MSR); in uic_get_irq()
/linux/arch/powerpc/boot/
A D4xx.c297 while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) in ibm4xx_quiesce_eth()
313 bxcr = mfdcr(DCRN_EBC0_CFGDATA); in ibm4xx_fixup_ebc_ranges()
333 u32 sys0 = mfdcr(DCRN_CPC0_SYS0); in ibm440gp_fixup_clocks()
334 u32 cr0 = mfdcr(DCRN_CPC0_CR0); in ibm440gp_fixup_clocks()
550 u32 pllmr = mfdcr(DCRN_CPC0_PLLMR); in ibm405gp_fixup_clocks()
551 u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0); in ibm405gp_fixup_clocks()
552 u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1); in ibm405gp_fixup_clocks()
553 u32 psr = mfdcr(DCRN_405_CPC0_PSR); in ibm405gp_fixup_clocks()
623 u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0); in ibm405ep_fixup_clocks()
624 u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1); in ibm405ep_fixup_clocks()
[all …]
A Ddcr.h5 #define mfdcr(rn) \ macro
30 mfdcr(DCRN_SDRAM0_CFGDATA); })
183 mfdcr(DCRN_SDR0_CONFIG_DATA); })
201 mfdcr(DCRN_CPR0_CFGDATA); })
A Dcuboot-hotfoot.c26 u32 uart = mfdcr(DCRN_CPC0_UCR) & 0x7f; in hotfoot_fixups()
/linux/arch/powerpc/sysdev/
A Ddcr-low.S35 mfdcr r3,0; blr
41 mfdcr r3,dcr; blr
/linux/arch/powerpc/include/asm/
A Ddcr-native.h29 #define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
53 #define mfdcr(rn) \ macro
/linux/arch/powerpc/kernel/
A Dcpu_setup_44x.S63 mfdcr r3,DCRN_PLB4A0_ACR

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