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Searched refs:mg_pll_div0 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
A Dintel_dpll_mgr.c2911 pll_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) | in icl_calc_mg_pll_state()
2932 pll_state->mg_pll_div0 = in icl_calc_mg_pll_state()
3011 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()
3013 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; in icl_ddi_mg_pll_get_freq()
3024 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; in icl_ddi_mg_pll_get_freq()
3026 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { in icl_ddi_mg_pll_get_freq()
3027 m2_frac = pll_state->mg_pll_div0 & in icl_ddi_mg_pll_get_freq()
3342 hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port)); in mg_pll_get_hw_state()
3414 hw_state->mg_pll_div0 &= (DKL_PLL_DIV0_INTEG_COEFF_MASK | in dkl_pll_get_hw_state()
3638 val |= hw_state->mg_pll_div0; in dkl_pll_write()
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A Dintel_dpll_mgr.h220 u32 mg_pll_div0; member
A Dintel_display_debugfs.c1122 pll->state.hw_state.mg_pll_div0); in i915_shared_dplls_info()
A Dintel_display.c7757 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); in intel_pipe_config_compare()

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