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Searched refs:mg_pll_div1 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
A Dintel_dpll_mgr.h221 u32 mg_pll_div1; member
A Dintel_dpll_mgr.c2916 pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) | in icl_calc_mg_pll_state()
2937 pll_state->mg_pll_div1 = in icl_calc_mg_pll_state()
3023 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()
3343 hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()
3419 hw_state->mg_pll_div1 = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()
3420 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | in dkl_pll_get_hw_state()
3581 intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()
3644 val |= hw_state->mg_pll_div1; in dkl_pll_write()
3889 hw_state->mg_pll_div1, in icl_dump_hw_state()
A Dintel_display_debugfs.c1124 pll->state.hw_state.mg_pll_div1); in i915_shared_dplls_info()
A Dintel_display.c7758 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); in intel_pipe_config_compare()

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