| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | dml1_display_rq_dlg_calc.c | 1026 double min_ttu_vblank; in dml1_rq_dlg_get_dlg_params() local
1165 min_ttu_vblank = dlg_sys_param->t_urg_wm_us; in dml1_rq_dlg_get_dlg_params()
1167 min_ttu_vblank = dml_max(dlg_sys_param->t_sr_wm_us, min_ttu_vblank); in dml1_rq_dlg_get_dlg_params()
1169 min_ttu_vblank = dml_max(dlg_sys_param->t_mclk_wm_us, min_ttu_vblank); in dml1_rq_dlg_get_dlg_params()
1170 min_ttu_vblank = min_ttu_vblank + t_calc_us; in dml1_rq_dlg_get_dlg_params()
1172 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml1_rq_dlg_get_dlg_params()
1180 DTRACE("DLG: %s: min_ttu_vblank = %3.2f", __func__, min_ttu_vblank); in dml1_rq_dlg_get_dlg_params()
1927 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml1_rq_dlg_get_dlg_params()
1928 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml1_rq_dlg_get_dlg_params()
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| A D | display_rq_dlg_helpers.c | 343 ttu_regs->min_ttu_vblank); in print__ttu_regs_st()
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| A D | display_mode_structs.h | 500 unsigned int min_ttu_vblank; member
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| A D | display_mode_vba.h | 67 dml_get_pipe_attr_decl(min_ttu_vblank);
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| A D | display_mode_vba.c | 123 dml_get_pipe_attr_func(min_ttu_vblank, mode_lib->vba.MinTTUVBlank);
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer_debug.c | 156 … (s->min_ttu_vblank * frac) / ref_clk_mhz / frac, (s->min_ttu_vblank * frac) / ref_clk_mhz % frac, in dcn10_get_hubp_states()
176 … (s->min_ttu_vblank * frac) / ref_clk_mhz / frac, (s->min_ttu_vblank * frac) / ref_clk_mhz % frac, in dcn10_get_hubp_states()
311 …>hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank, in dcn10_get_ttu_states()
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| A D | dcn10_hubp.c | 727 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, in hubp1_setup_interdependent()
995 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, in hubp1_read_state_common()
1052 MIN_TTU_VBLANK, &s->min_ttu_vblank); in hubp1_read_state_common()
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| A D | dcn10_hubp.h | 682 uint32_t min_ttu_vblank; member
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| A D | dcn10_hw_sequencer.c | 192 DTN_INFO_MICRO_SEC(s->min_ttu_vblank); in dcn10_log_hubp_states()
266 …>hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank, in dcn10_log_hubp_states()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.c | 823 double min_ttu_vblank; in dml20_rq_dlg_get_dlg_params() local
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
942 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml20_rq_dlg_get_dlg_params()
953 min_ttu_vblank); in dml20_rq_dlg_get_dlg_params()
1542 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml20_rq_dlg_get_dlg_params()
1543 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml20_rq_dlg_get_dlg_params()
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| A D | display_rq_dlg_calc_20v2.c | 823 double min_ttu_vblank; in dml20v2_rq_dlg_get_dlg_params() local
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
942 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml20v2_rq_dlg_get_dlg_params()
954 min_ttu_vblank); in dml20v2_rq_dlg_get_dlg_params()
1543 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml20v2_rq_dlg_get_dlg_params()
1544 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml20v2_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 869 double min_ttu_vblank; in dml_rq_dlg_get_dlg_params() local
986 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
988 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml_rq_dlg_get_dlg_params()
1001 min_ttu_vblank); in dml_rq_dlg_get_dlg_params()
1650 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml_rq_dlg_get_dlg_params()
1651 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 1023 double min_ttu_vblank = 0; in dml_rq_dlg_get_dlg_params() local
1142 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1144 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double)htotal; in dml_rq_dlg_get_dlg_params()
1156 min_ttu_vblank); in dml_rq_dlg_get_dlg_params()
1824 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml_rq_dlg_get_dlg_params()
1825 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 976 double min_ttu_vblank; in dml_rq_dlg_get_dlg_params() local
1078 …min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From … in dml_rq_dlg_get_dlg_params()
1085 dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); in dml_rq_dlg_get_dlg_params()
1669 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; in dml_rq_dlg_get_dlg_params()
1670 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_hubp.c | 292 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, in hubp2_setup_interdependent()
1182 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, in hubp2_read_state_common()
1239 MIN_TTU_VBLANK, &s->min_ttu_vblank); in hubp2_read_state_common()
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| A D | dcn20_hwseq.c | 1372 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || in dcn20_detect_pipe_changes()
1390 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; in dcn20_detect_pipe_changes()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc.c | 2868 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU; in commit_planes_for_stream()
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