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/linux/arch/powerpc/perf/
A Dpower8-pmu.c128 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
130 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
137 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
142 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
145 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
148 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
150 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
151 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
A Dgeneric-compat-pmu.c106 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
107 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
109 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
110 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
111 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
112 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
113 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
114 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
115 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
A Dpower10-pmu.c124 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
126 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
130 GENERIC_EVENT_ATTR(branch-misses, PM_MPRED_BR_FIN);
131 GENERIC_EVENT_ATTR(cache-misses, PM_LD_DEMAND_MISS_L1_FIN);
133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
136 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
140 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
143 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
145 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
147 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
[all …]
A Dpower9-pmu.c171 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
173 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN);
177 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
180 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
181 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
184 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
187 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
189 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
190 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
A Dpower7-pmu.c383 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
385 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED);
/linux/tools/perf/tests/attr/
A Dtest-record-group-sampling3 args = --no-bpf-event -e '{cycles,cache-misses}:S' kill >/dev/null 2>&1
17 # cache-misses
/linux/drivers/video/fbdev/riva/
A Driva_hw.c249 int misses; in nv3_iterate() local
333 if (last==cur) misses = 0; in nv3_iterate()
334 else if (ainfo->first_vacc) misses = vmisses; in nv3_iterate()
335 else misses = 1; in nv3_iterate()
349 if (last==cur) misses = 0; in nv3_iterate()
350 else if (ainfo->first_gacc) misses = gmisses; in nv3_iterate()
351 else misses = 1; in nv3_iterate()
365 if (last==cur) misses = 0; in nv3_iterate()
366 else if (ainfo->first_macc) misses = mmisses; in nv3_iterate()
367 else misses = 1; in nv3_iterate()
[all …]
/linux/tools/perf/util/
A Dparse-events.l338 cache-misses { return sym(yyscanner, PERF_TYPE_HARDWARE, PERF_COUNT_HW_CACHE_MISSES); }
340 branch-misses { return sym(yyscanner, PERF_TYPE_HARDWARE, PERF_COUNT_HW_BRANCH_MISSES); }
384 misses|miss { return str(yyscanner, PE_NAME_CACHE_OP_RESULT); }
/linux/Documentation/devicetree/bindings/perf/
A Dnds32v3-pmu.txt3 NDS32 core have a PMU for counting cpu and cache events like cache misses.
/linux/Documentation/devicetree/bindings/arc/
A Darchs-pct.txt4 CPU and cache events like cache misses and hits. Like conventional PCT there
A Dpct.txt4 CPU and cache events like cache misses and hits. Like conventional PCT there
/linux/Documentation/ABI/testing/
A Dsysfs-bus-event_source-devices-events2 /sys/devices/cpu/events/branch-misses
4 /sys/devices/cpu/events/cache-misses
/linux/drivers/md/
A Ddm-cache-policy-smq.c517 unsigned misses; member
530 s->misses = 0u; in stats_init()
535 s->hits = s->misses = 0u; in stats_reset()
543 s->misses++; in stats_level_accessed()
548 s->misses++; in stats_miss()
559 unsigned confidence = safe_div(s->hits << FP_SHIFT, s->hits + s->misses); in stats_assess()
1032 unsigned misses = mq->cache_stats.misses; in default_promote_level() local
1033 unsigned index = safe_div(hits << 4u, hits + misses); in default_promote_level()
/linux/lib/
A Dlru_cache.c204 lc->misses = 0; in lc_reset()
241 lc->hits, lc->misses, lc->starving, lc->locked, lc->changed); in lc_seq_printf_stats()
400 ++lc->misses; in __lc_get()
/linux/include/linux/
A Dlru_cache.h196 unsigned long hits, misses, starving, locked, changed; member
/linux/security/selinux/include/
A Davc.h38 unsigned int misses; member
/linux/drivers/net/ethernet/myricom/
A DKconfig43 is used, with the intent of lessening the impact of cache misses.
/linux/tools/perf/Documentation/
A Dintel-hybrid.txt198 cpu_core/branch-misses/,
199 cpu_atom/branch-misses/
A Ditrace.txt2 b synthesize branches events (branch misses for Arm SPE)
/linux/Documentation/admin-guide/device-mapper/
A Dcache.rst240 <#read hits> <#read misses> <#write hits> <#write misses>
257 #read misses Number of times a READ bio has been mapped
261 #write misses Number of times a WRITE bio has been
/linux/Documentation/staging/
A Dstatic-keys.rst307 5,569,188 branch-misses # 2.67% of all branches ( +- 0.54% )
324 4,884,119 branch-misses # 2.36% of all branches ( +- 0.85% )
329 'branch-misses'. This is where we would expect to get the most savings, since
/linux/Documentation/virt/
A Dguest-halt-polling.rst60 be increased from 10000, to avoid misses during the initial
/linux/Documentation/admin-guide/
A Dbcache.rst367 - Traffic's still going to the spindle/still getting cache misses
385 - Still getting cache misses, of the same data
388 the way cache coherency is handled for cache misses. If a btree node is full,
499 Hits and misses are counted per individual IO as bcache sees them; a
503 Hits and misses for IO that is intended to skip the cache are still counted,
509 since the synchronization for cache misses was rewritten)
/linux/Documentation/devicetree/bindings/arm/
A Dpmu.yaml14 ARM cores often have a PMU for counting cpu and cache events like cache misses
/linux/Documentation/hwmon/
A Dlm63.rst51 capabilities added. It misses some of the LM86 features though:

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