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Searched refs:mmCPU_PLL_DIV_SEL_0 (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/misc/habanalabs/include/goya/asic_reg/
A Dcpu_pll_regs.h60 #define mmCPU_PLL_DIV_SEL_0 0x4A2280 macro
/linux/drivers/misc/habanalabs/goya/
A Dgoya.c1326 WREG32(mmCPU_PLL_DIV_SEL_0, 0x0); in goya_set_pll_refclk()

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