1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DMA_CH_1_REGS_H_ 14 #define ASIC_REG_DMA_CH_1_REGS_H_ 15 16 /* 17 ***************************************** 18 * DMA_CH_1 (Prototype: DMA_CH) 19 ***************************************** 20 */ 21 22 #define mmDMA_CH_1_CFG0 0x409000 23 24 #define mmDMA_CH_1_CFG1 0x409004 25 26 #define mmDMA_CH_1_ERRMSG_ADDR_LO 0x409008 27 28 #define mmDMA_CH_1_ERRMSG_ADDR_HI 0x40900C 29 30 #define mmDMA_CH_1_ERRMSG_WDATA 0x409010 31 32 #define mmDMA_CH_1_RD_COMP_ADDR_LO 0x409014 33 34 #define mmDMA_CH_1_RD_COMP_ADDR_HI 0x409018 35 36 #define mmDMA_CH_1_RD_COMP_WDATA 0x40901C 37 38 #define mmDMA_CH_1_WR_COMP_ADDR_LO 0x409020 39 40 #define mmDMA_CH_1_WR_COMP_ADDR_HI 0x409024 41 42 #define mmDMA_CH_1_WR_COMP_WDATA 0x409028 43 44 #define mmDMA_CH_1_LDMA_SRC_ADDR_LO 0x40902C 45 46 #define mmDMA_CH_1_LDMA_SRC_ADDR_HI 0x409030 47 48 #define mmDMA_CH_1_LDMA_DST_ADDR_LO 0x409034 49 50 #define mmDMA_CH_1_LDMA_DST_ADDR_HI 0x409038 51 52 #define mmDMA_CH_1_LDMA_TSIZE 0x40903C 53 54 #define mmDMA_CH_1_COMIT_TRANSFER 0x409040 55 56 #define mmDMA_CH_1_STS0 0x409044 57 58 #define mmDMA_CH_1_STS1 0x409048 59 60 #define mmDMA_CH_1_STS2 0x40904C 61 62 #define mmDMA_CH_1_STS3 0x409050 63 64 #define mmDMA_CH_1_STS4 0x409054 65 66 #define mmDMA_CH_1_SRC_ADDR_LO_STS 0x409058 67 68 #define mmDMA_CH_1_SRC_ADDR_HI_STS 0x40905C 69 70 #define mmDMA_CH_1_SRC_TSIZE_STS 0x409060 71 72 #define mmDMA_CH_1_DST_ADDR_LO_STS 0x409064 73 74 #define mmDMA_CH_1_DST_ADDR_HI_STS 0x409068 75 76 #define mmDMA_CH_1_DST_TSIZE_STS 0x40906C 77 78 #define mmDMA_CH_1_RD_RATE_LIM_EN 0x409070 79 80 #define mmDMA_CH_1_RD_RATE_LIM_RST_TOKEN 0x409074 81 82 #define mmDMA_CH_1_RD_RATE_LIM_SAT 0x409078 83 84 #define mmDMA_CH_1_RD_RATE_LIM_TOUT 0x40907C 85 86 #define mmDMA_CH_1_WR_RATE_LIM_EN 0x409080 87 88 #define mmDMA_CH_1_WR_RATE_LIM_RST_TOKEN 0x409084 89 90 #define mmDMA_CH_1_WR_RATE_LIM_SAT 0x409088 91 92 #define mmDMA_CH_1_WR_RATE_LIM_TOUT 0x40908C 93 94 #define mmDMA_CH_1_CFG2 0x409090 95 96 #define mmDMA_CH_1_TDMA_CTL 0x409100 97 98 #define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_LO 0x409104 99 100 #define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_HI 0x409108 101 102 #define mmDMA_CH_1_TDMA_SRC_ROI_BASE_0 0x40910C 103 104 #define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_0 0x409110 105 106 #define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_0 0x409114 107 108 #define mmDMA_CH_1_TDMA_SRC_START_OFFSET_0 0x409118 109 110 #define mmDMA_CH_1_TDMA_SRC_STRIDE_0 0x40911C 111 112 #define mmDMA_CH_1_TDMA_SRC_ROI_BASE_1 0x409120 113 114 #define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_1 0x409124 115 116 #define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_1 0x409128 117 118 #define mmDMA_CH_1_TDMA_SRC_START_OFFSET_1 0x40912C 119 120 #define mmDMA_CH_1_TDMA_SRC_STRIDE_1 0x409130 121 122 #define mmDMA_CH_1_TDMA_SRC_ROI_BASE_2 0x409134 123 124 #define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_2 0x409138 125 126 #define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_2 0x40913C 127 128 #define mmDMA_CH_1_TDMA_SRC_START_OFFSET_2 0x409140 129 130 #define mmDMA_CH_1_TDMA_SRC_STRIDE_2 0x409144 131 132 #define mmDMA_CH_1_TDMA_SRC_ROI_BASE_3 0x409148 133 134 #define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_3 0x40914C 135 136 #define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_3 0x409150 137 138 #define mmDMA_CH_1_TDMA_SRC_START_OFFSET_3 0x409154 139 140 #define mmDMA_CH_1_TDMA_SRC_STRIDE_3 0x409158 141 142 #define mmDMA_CH_1_TDMA_SRC_ROI_BASE_4 0x40915C 143 144 #define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_4 0x409160 145 146 #define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_4 0x409164 147 148 #define mmDMA_CH_1_TDMA_SRC_START_OFFSET_4 0x409168 149 150 #define mmDMA_CH_1_TDMA_SRC_STRIDE_4 0x40916C 151 152 #define mmDMA_CH_1_TDMA_DST_BASE_ADDR_LO 0x409170 153 154 #define mmDMA_CH_1_TDMA_DST_BASE_ADDR_HI 0x409174 155 156 #define mmDMA_CH_1_TDMA_DST_ROI_BASE_0 0x409178 157 158 #define mmDMA_CH_1_TDMA_DST_ROI_SIZE_0 0x40917C 159 160 #define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_0 0x409180 161 162 #define mmDMA_CH_1_TDMA_DST_START_OFFSET_0 0x409184 163 164 #define mmDMA_CH_1_TDMA_DST_STRIDE_0 0x409188 165 166 #define mmDMA_CH_1_TDMA_DST_ROI_BASE_1 0x40918C 167 168 #define mmDMA_CH_1_TDMA_DST_ROI_SIZE_1 0x409190 169 170 #define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_1 0x409194 171 172 #define mmDMA_CH_1_TDMA_DST_START_OFFSET_1 0x409198 173 174 #define mmDMA_CH_1_TDMA_DST_STRIDE_1 0x40919C 175 176 #define mmDMA_CH_1_TDMA_DST_ROI_BASE_2 0x4091A0 177 178 #define mmDMA_CH_1_TDMA_DST_ROI_SIZE_2 0x4091A4 179 180 #define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_2 0x4091A8 181 182 #define mmDMA_CH_1_TDMA_DST_START_OFFSET_2 0x4091AC 183 184 #define mmDMA_CH_1_TDMA_DST_STRIDE_2 0x4091B0 185 186 #define mmDMA_CH_1_TDMA_DST_ROI_BASE_3 0x4091B4 187 188 #define mmDMA_CH_1_TDMA_DST_ROI_SIZE_3 0x4091B8 189 190 #define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_3 0x4091BC 191 192 #define mmDMA_CH_1_TDMA_DST_START_OFFSET_3 0x4091C0 193 194 #define mmDMA_CH_1_TDMA_DST_STRIDE_3 0x4091C4 195 196 #define mmDMA_CH_1_TDMA_DST_ROI_BASE_4 0x4091C8 197 198 #define mmDMA_CH_1_TDMA_DST_ROI_SIZE_4 0x4091CC 199 200 #define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_4 0x4091D0 201 202 #define mmDMA_CH_1_TDMA_DST_START_OFFSET_4 0x4091D4 203 204 #define mmDMA_CH_1_TDMA_DST_STRIDE_4 0x4091D8 205 206 #define mmDMA_CH_1_MEM_INIT_BUSY 0x4091FC 207 208 #endif /* ASIC_REG_DMA_CH_1_REGS_H_ */ 209