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Searched refs:mmMP1_SMN_C2PMSG_82 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dsmu9_smumgr.c154 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); in smu9_send_msg_to_smc_with_parameter()
173 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu9_get_argument()
A Dsmu10_smumgr.c76 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu10_read_arg_from_smc()
105 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); in smu10_send_msg_to_smc_with_parameter()
A Dvega20_smumgr.c140 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); in vega20_send_msg_to_smc_with_parameter()
155 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in vega20_get_argument()
/linux/drivers/gpu/drm/amd/pm/swsmu/
A Dsmu_cmn.c48 #define mmMP1_SMN_C2PMSG_82 macro
76 *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu_cmn_read_arg()
144 u32 prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in __smu_cmn_reg_print_error()
239 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param); in __smu_cmn_send_msg()
/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
A Dmp_10_0_offset.h282 #define mmMP1_SMN_C2PMSG_82 macro
A Dmp_12_0_0_offset.h282 #define mmMP1_SMN_C2PMSG_82 macro
A Dmp_11_0_offset.h284 #define mmMP1_SMN_C2PMSG_82 macro
A Dmp_11_0_8_offset.h282 #define mmMP1_SMN_C2PMSG_82 macro
A Dmp_9_0_offset.h294 #define mmMP1_SMN_C2PMSG_82 0x0292 macro
A Dmp_11_5_0_offset.h282 #define mmMP1_SMN_C2PMSG_82 macro

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