1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_PCI_NRTR_REGS_H_ 14 #define ASIC_REG_PCI_NRTR_REGS_H_ 15 16 /* 17 ***************************************** 18 * PCI_NRTR (Prototype: IF_NRTR) 19 ***************************************** 20 */ 21 22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100 23 24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120 25 26 #define mmPCI_NRTR_DBG_E_ARB 0x300 27 28 #define mmPCI_NRTR_DBG_W_ARB 0x304 29 30 #define mmPCI_NRTR_DBG_N_ARB 0x308 31 32 #define mmPCI_NRTR_DBG_S_ARB 0x30C 33 34 #define mmPCI_NRTR_DBG_L_ARB 0x310 35 36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320 37 38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324 39 40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328 41 42 #define mmPCI_NRTR_DBG_S_ARB_MAX 0x32C 43 44 #define mmPCI_NRTR_DBG_L_ARB_MAX 0x330 45 46 #define mmPCI_NRTR_SPLIT_COEF_0 0x400 47 48 #define mmPCI_NRTR_SPLIT_COEF_1 0x404 49 50 #define mmPCI_NRTR_SPLIT_COEF_2 0x408 51 52 #define mmPCI_NRTR_SPLIT_COEF_3 0x40C 53 54 #define mmPCI_NRTR_SPLIT_COEF_4 0x410 55 56 #define mmPCI_NRTR_SPLIT_COEF_5 0x414 57 58 #define mmPCI_NRTR_SPLIT_COEF_6 0x418 59 60 #define mmPCI_NRTR_SPLIT_COEF_7 0x41C 61 62 #define mmPCI_NRTR_SPLIT_COEF_8 0x420 63 64 #define mmPCI_NRTR_SPLIT_COEF_9 0x424 65 66 #define mmPCI_NRTR_SPLIT_CFG 0x440 67 68 #define mmPCI_NRTR_SPLIT_RD_SAT 0x444 69 70 #define mmPCI_NRTR_SPLIT_RD_RST_TOKEN 0x448 71 72 #define mmPCI_NRTR_SPLIT_RD_TIMEOUT_0 0x44C 73 74 #define mmPCI_NRTR_SPLIT_RD_TIMEOUT_1 0x450 75 76 #define mmPCI_NRTR_SPLIT_WR_SAT 0x454 77 78 #define mmPCI_NRTR_WPLIT_WR_TST_TOLEN 0x458 79 80 #define mmPCI_NRTR_SPLIT_WR_TIMEOUT_0 0x45C 81 82 #define mmPCI_NRTR_SPLIT_WR_TIMEOUT_1 0x460 83 84 #define mmPCI_NRTR_HBW_RANGE_HIT 0x470 85 86 #define mmPCI_NRTR_HBW_RANGE_MASK_L_0 0x480 87 88 #define mmPCI_NRTR_HBW_RANGE_MASK_L_1 0x484 89 90 #define mmPCI_NRTR_HBW_RANGE_MASK_L_2 0x488 91 92 #define mmPCI_NRTR_HBW_RANGE_MASK_L_3 0x48C 93 94 #define mmPCI_NRTR_HBW_RANGE_MASK_L_4 0x490 95 96 #define mmPCI_NRTR_HBW_RANGE_MASK_L_5 0x494 97 98 #define mmPCI_NRTR_HBW_RANGE_MASK_L_6 0x498 99 100 #define mmPCI_NRTR_HBW_RANGE_MASK_L_7 0x49C 101 102 #define mmPCI_NRTR_HBW_RANGE_MASK_H_0 0x4A0 103 104 #define mmPCI_NRTR_HBW_RANGE_MASK_H_1 0x4A4 105 106 #define mmPCI_NRTR_HBW_RANGE_MASK_H_2 0x4A8 107 108 #define mmPCI_NRTR_HBW_RANGE_MASK_H_3 0x4AC 109 110 #define mmPCI_NRTR_HBW_RANGE_MASK_H_4 0x4B0 111 112 #define mmPCI_NRTR_HBW_RANGE_MASK_H_5 0x4B4 113 114 #define mmPCI_NRTR_HBW_RANGE_MASK_H_6 0x4B8 115 116 #define mmPCI_NRTR_HBW_RANGE_MASK_H_7 0x4BC 117 118 #define mmPCI_NRTR_HBW_RANGE_BASE_L_0 0x4C0 119 120 #define mmPCI_NRTR_HBW_RANGE_BASE_L_1 0x4C4 121 122 #define mmPCI_NRTR_HBW_RANGE_BASE_L_2 0x4C8 123 124 #define mmPCI_NRTR_HBW_RANGE_BASE_L_3 0x4CC 125 126 #define mmPCI_NRTR_HBW_RANGE_BASE_L_4 0x4D0 127 128 #define mmPCI_NRTR_HBW_RANGE_BASE_L_5 0x4D4 129 130 #define mmPCI_NRTR_HBW_RANGE_BASE_L_6 0x4D8 131 132 #define mmPCI_NRTR_HBW_RANGE_BASE_L_7 0x4DC 133 134 #define mmPCI_NRTR_HBW_RANGE_BASE_H_0 0x4E0 135 136 #define mmPCI_NRTR_HBW_RANGE_BASE_H_1 0x4E4 137 138 #define mmPCI_NRTR_HBW_RANGE_BASE_H_2 0x4E8 139 140 #define mmPCI_NRTR_HBW_RANGE_BASE_H_3 0x4EC 141 142 #define mmPCI_NRTR_HBW_RANGE_BASE_H_4 0x4F0 143 144 #define mmPCI_NRTR_HBW_RANGE_BASE_H_5 0x4F4 145 146 #define mmPCI_NRTR_HBW_RANGE_BASE_H_6 0x4F8 147 148 #define mmPCI_NRTR_HBW_RANGE_BASE_H_7 0x4FC 149 150 #define mmPCI_NRTR_LBW_RANGE_HIT 0x500 151 152 #define mmPCI_NRTR_LBW_RANGE_MASK_0 0x510 153 154 #define mmPCI_NRTR_LBW_RANGE_MASK_1 0x514 155 156 #define mmPCI_NRTR_LBW_RANGE_MASK_2 0x518 157 158 #define mmPCI_NRTR_LBW_RANGE_MASK_3 0x51C 159 160 #define mmPCI_NRTR_LBW_RANGE_MASK_4 0x520 161 162 #define mmPCI_NRTR_LBW_RANGE_MASK_5 0x524 163 164 #define mmPCI_NRTR_LBW_RANGE_MASK_6 0x528 165 166 #define mmPCI_NRTR_LBW_RANGE_MASK_7 0x52C 167 168 #define mmPCI_NRTR_LBW_RANGE_MASK_8 0x530 169 170 #define mmPCI_NRTR_LBW_RANGE_MASK_9 0x534 171 172 #define mmPCI_NRTR_LBW_RANGE_MASK_10 0x538 173 174 #define mmPCI_NRTR_LBW_RANGE_MASK_11 0x53C 175 176 #define mmPCI_NRTR_LBW_RANGE_MASK_12 0x540 177 178 #define mmPCI_NRTR_LBW_RANGE_MASK_13 0x544 179 180 #define mmPCI_NRTR_LBW_RANGE_MASK_14 0x548 181 182 #define mmPCI_NRTR_LBW_RANGE_MASK_15 0x54C 183 184 #define mmPCI_NRTR_LBW_RANGE_BASE_0 0x550 185 186 #define mmPCI_NRTR_LBW_RANGE_BASE_1 0x554 187 188 #define mmPCI_NRTR_LBW_RANGE_BASE_2 0x558 189 190 #define mmPCI_NRTR_LBW_RANGE_BASE_3 0x55C 191 192 #define mmPCI_NRTR_LBW_RANGE_BASE_4 0x560 193 194 #define mmPCI_NRTR_LBW_RANGE_BASE_5 0x564 195 196 #define mmPCI_NRTR_LBW_RANGE_BASE_6 0x568 197 198 #define mmPCI_NRTR_LBW_RANGE_BASE_7 0x56C 199 200 #define mmPCI_NRTR_LBW_RANGE_BASE_8 0x570 201 202 #define mmPCI_NRTR_LBW_RANGE_BASE_9 0x574 203 204 #define mmPCI_NRTR_LBW_RANGE_BASE_10 0x578 205 206 #define mmPCI_NRTR_LBW_RANGE_BASE_11 0x57C 207 208 #define mmPCI_NRTR_LBW_RANGE_BASE_12 0x580 209 210 #define mmPCI_NRTR_LBW_RANGE_BASE_13 0x584 211 212 #define mmPCI_NRTR_LBW_RANGE_BASE_14 0x588 213 214 #define mmPCI_NRTR_LBW_RANGE_BASE_15 0x58C 215 216 #define mmPCI_NRTR_RGLTR 0x590 217 218 #define mmPCI_NRTR_RGLTR_WR_RESULT 0x594 219 220 #define mmPCI_NRTR_RGLTR_RD_RESULT 0x598 221 222 #define mmPCI_NRTR_SCRAMB_EN 0x600 223 224 #define mmPCI_NRTR_NON_LIN_SCRAMB 0x604 225 226 #endif /* ASIC_REG_PCI_NRTR_REGS_H_ */ 227