1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_PSOC_MME_PLL_REGS_H_ 14 #define ASIC_REG_PSOC_MME_PLL_REGS_H_ 15 16 /* 17 ***************************************** 18 * PSOC_MME_PLL (Prototype: PLL) 19 ***************************************** 20 */ 21 22 #define mmPSOC_MME_PLL_NR 0xC71100 23 24 #define mmPSOC_MME_PLL_NF 0xC71104 25 26 #define mmPSOC_MME_PLL_OD 0xC71108 27 28 #define mmPSOC_MME_PLL_NB 0xC7110C 29 30 #define mmPSOC_MME_PLL_CFG 0xC71110 31 32 #define mmPSOC_MME_PLL_LOSE_MASK 0xC71120 33 34 #define mmPSOC_MME_PLL_LOCK_INTR 0xC71128 35 36 #define mmPSOC_MME_PLL_LOCK_BYPASS 0xC7112C 37 38 #define mmPSOC_MME_PLL_DATA_CHNG 0xC71130 39 40 #define mmPSOC_MME_PLL_RST 0xC71134 41 42 #define mmPSOC_MME_PLL_SLIP_WD_CNTR 0xC71150 43 44 #define mmPSOC_MME_PLL_DIV_FACTOR_0 0xC71200 45 46 #define mmPSOC_MME_PLL_DIV_FACTOR_1 0xC71204 47 48 #define mmPSOC_MME_PLL_DIV_FACTOR_2 0xC71208 49 50 #define mmPSOC_MME_PLL_DIV_FACTOR_3 0xC7120C 51 52 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_0 0xC71220 53 54 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_1 0xC71224 55 56 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_2 0xC71228 57 58 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_3 0xC7122C 59 60 #define mmPSOC_MME_PLL_DIV_SEL_0 0xC71280 61 62 #define mmPSOC_MME_PLL_DIV_SEL_1 0xC71284 63 64 #define mmPSOC_MME_PLL_DIV_SEL_2 0xC71288 65 66 #define mmPSOC_MME_PLL_DIV_SEL_3 0xC7128C 67 68 #define mmPSOC_MME_PLL_DIV_EN_0 0xC712A0 69 70 #define mmPSOC_MME_PLL_DIV_EN_1 0xC712A4 71 72 #define mmPSOC_MME_PLL_DIV_EN_2 0xC712A8 73 74 #define mmPSOC_MME_PLL_DIV_EN_3 0xC712AC 75 76 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_0 0xC712C0 77 78 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_1 0xC712C4 79 80 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_2 0xC712C8 81 82 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_3 0xC712CC 83 84 #define mmPSOC_MME_PLL_CLK_GATER 0xC71300 85 86 #define mmPSOC_MME_PLL_CLK_RLX_0 0xC71310 87 88 #define mmPSOC_MME_PLL_CLK_RLX_1 0xC71314 89 90 #define mmPSOC_MME_PLL_CLK_RLX_2 0xC71318 91 92 #define mmPSOC_MME_PLL_CLK_RLX_3 0xC7131C 93 94 #define mmPSOC_MME_PLL_REF_CNTR_PERIOD 0xC71400 95 96 #define mmPSOC_MME_PLL_REF_LOW_THRESHOLD 0xC71410 97 98 #define mmPSOC_MME_PLL_REF_HIGH_THRESHOLD 0xC71420 99 100 #define mmPSOC_MME_PLL_PLL_NOT_STABLE 0xC71430 101 102 #define mmPSOC_MME_PLL_FREQ_CALC_EN 0xC71440 103 104 #endif /* ASIC_REG_PSOC_MME_PLL_REGS_H_ */ 105