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Searched refs:mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
A Ddpcs_3_0_3_offset.h148 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX macro
A Ddpcs_3_0_0_offset.h141 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
A Ddpcs_2_1_0_offset.h175 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX macro
A Ddpcs_2_0_0_offset.h167 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX macro

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