1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2018 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_TPC0_EML_CFG_REGS_H_
14 #define ASIC_REG_TPC0_EML_CFG_REGS_H_
15 
16 /*
17  *****************************************
18  *   TPC0_EML_CFG (Prototype: TPC_EML_CFG)
19  *****************************************
20  */
21 
22 #define mmTPC0_EML_CFG_DBG_CNT                                       0x3040000
23 
24 #define mmTPC0_EML_CFG_DBG_STS                                       0x3040004
25 
26 #define mmTPC0_EML_CFG_DBG_PADD_0                                    0x3040008
27 
28 #define mmTPC0_EML_CFG_DBG_PADD_1                                    0x304000C
29 
30 #define mmTPC0_EML_CFG_DBG_PADD_2                                    0x3040010
31 
32 #define mmTPC0_EML_CFG_DBG_PADD_3                                    0x3040014
33 
34 #define mmTPC0_EML_CFG_DBG_PADD_4                                    0x3040018
35 
36 #define mmTPC0_EML_CFG_DBG_PADD_5                                    0x304001C
37 
38 #define mmTPC0_EML_CFG_DBG_PADD_6                                    0x3040020
39 
40 #define mmTPC0_EML_CFG_DBG_PADD_7                                    0x3040024
41 
42 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_0                              0x3040028
43 
44 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_1                              0x304002C
45 
46 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_2                              0x3040030
47 
48 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_3                              0x3040034
49 
50 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_4                              0x3040038
51 
52 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_5                              0x304003C
53 
54 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_6                              0x3040040
55 
56 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_7                              0x3040044
57 
58 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_0                        0x3040048
59 
60 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_1                        0x304004C
61 
62 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_2                        0x3040050
63 
64 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_3                        0x3040054
65 
66 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_4                        0x3040058
67 
68 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_5                        0x304005C
69 
70 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_6                        0x3040060
71 
72 #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_7                        0x3040064
73 
74 #define mmTPC0_EML_CFG_DBG_PADD_EN                                   0x3040068
75 
76 #define mmTPC0_EML_CFG_DBG_VPADD_HIGH_0                              0x304006C
77 
78 #define mmTPC0_EML_CFG_DBG_VPADD_HIGH_1                              0x3040070
79 
80 #define mmTPC0_EML_CFG_DBG_VPADD_LOW_0                               0x3040074
81 
82 #define mmTPC0_EML_CFG_DBG_VPADD_LOW_1                               0x3040078
83 
84 #define mmTPC0_EML_CFG_DBG_VPADD_COUNT_0                             0x304007C
85 
86 #define mmTPC0_EML_CFG_DBG_VPADD_COUNT_1                             0x3040080
87 
88 #define mmTPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_0                       0x3040084
89 
90 #define mmTPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_1                       0x3040088
91 
92 #define mmTPC0_EML_CFG_DBG_VPADD_EN                                  0x304008C
93 
94 #define mmTPC0_EML_CFG_DBG_SPADD_HIGH_0                              0x3040090
95 
96 #define mmTPC0_EML_CFG_DBG_SPADD_HIGH_1                              0x3040094
97 
98 #define mmTPC0_EML_CFG_DBG_SPADD_LOW_0                               0x3040098
99 
100 #define mmTPC0_EML_CFG_DBG_SPADD_LOW_1                               0x304009C
101 
102 #define mmTPC0_EML_CFG_DBG_SPADD_COUNT_0                             0x30400A0
103 
104 #define mmTPC0_EML_CFG_DBG_SPADD_COUNT_1                             0x30400A4
105 
106 #define mmTPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_0                       0x30400A8
107 
108 #define mmTPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_1                       0x30400AC
109 
110 #define mmTPC0_EML_CFG_DBG_SPADD_EN                                  0x30400B0
111 
112 #define mmTPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_0                         0x30400B4
113 
114 #define mmTPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_1                         0x30400B8
115 
116 #define mmTPC0_EML_CFG_DBG_AGUADD_MSB_LOW_0                          0x30400BC
117 
118 #define mmTPC0_EML_CFG_DBG_AGUADD_MSB_LOW_1                          0x30400C0
119 
120 #define mmTPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_0                         0x30400C4
121 
122 #define mmTPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_1                         0x30400C8
123 
124 #define mmTPC0_EML_CFG_DBG_AGUADD_LSB_LOW_0                          0x30400CC
125 
126 #define mmTPC0_EML_CFG_DBG_AGUADD_LSB_LOW_1                          0x30400D0
127 
128 #define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_0                            0x30400D4
129 
130 #define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_1                            0x30400D8
131 
132 #define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_0                      0x30400DC
133 
134 #define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_1                      0x30400E0
135 
136 #define mmTPC0_EML_CFG_DBG_AGUADD_EN                                 0x30400E4
137 
138 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_0                      0x30400E8
139 
140 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_1                      0x30400EC
141 
142 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_0                       0x30400F0
143 
144 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_1                       0x30400F4
145 
146 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_0                      0x30400F8
147 
148 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_1                      0x30400FC
149 
150 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_0                       0x3040100
151 
152 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_1                       0x3040104
153 
154 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_0                         0x3040108
155 
156 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_1                         0x304010C
157 
158 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_0                   0x3040110
159 
160 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_1                   0x3040114
161 
162 #define mmTPC0_EML_CFG_DBG_AXIHBWADD_EN                              0x3040118
163 
164 #define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_0                      0x304011C
165 
166 #define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_1                      0x3040120
167 
168 #define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_0                       0x3040124
169 
170 #define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_1                       0x3040128
171 
172 #define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_0                      0x304012C
173 
174 #define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_1                      0x3040130
175 
176 #define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_0                       0x3040134
177 
178 #define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_1                       0x3040138
179 
180 #define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_0                         0x304013C
181 
182 #define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_1                         0x3040140
183 
184 #define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_0                   0x3040144
185 
186 #define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_1                   0x3040148
187 
188 #define mmTPC0_EML_CFG_DBG_AXILBWADD_EN                              0x304014C
189 
190 #define mmTPC0_EML_CFG_DBG_SPDATA_0                                  0x3040150
191 
192 #define mmTPC0_EML_CFG_DBG_SPDATA_1                                  0x3040154
193 
194 #define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_0                            0x3040158
195 
196 #define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_1                            0x304015C
197 
198 #define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_0                      0x3040160
199 
200 #define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_1                      0x3040164
201 
202 #define mmTPC0_EML_CFG_DBG_SPDATA_EN                                 0x3040168
203 
204 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_0                              0x304016C
205 
206 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_1                              0x3040170
207 
208 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_2                              0x3040174
209 
210 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_3                              0x3040178
211 
212 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_4                              0x304017C
213 
214 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_5                              0x3040180
215 
216 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_6                              0x3040184
217 
218 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_7                              0x3040188
219 
220 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_8                              0x304018C
221 
222 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_9                              0x3040190
223 
224 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_10                             0x3040194
225 
226 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_11                             0x3040198
227 
228 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_12                             0x304019C
229 
230 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_13                             0x30401A0
231 
232 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_14                             0x30401A4
233 
234 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_15                             0x30401A8
235 
236 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_16                             0x30401AC
237 
238 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_17                             0x30401B0
239 
240 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_18                             0x30401B4
241 
242 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_19                             0x30401B8
243 
244 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_20                             0x30401BC
245 
246 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_21                             0x30401C0
247 
248 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_22                             0x30401C4
249 
250 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_23                             0x30401C8
251 
252 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_24                             0x30401CC
253 
254 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_25                             0x30401D0
255 
256 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_26                             0x30401D4
257 
258 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_27                             0x30401D8
259 
260 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_28                             0x30401DC
261 
262 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_29                             0x30401E0
263 
264 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_30                             0x30401E4
265 
266 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_31                             0x30401E8
267 
268 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_COUNT                          0x30401EC
269 
270 #define mmTPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH                     0x30401F0
271 
272 #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_EN                             0x30401F4
273 
274 #define mmTPC0_EML_CFG_DBG_AXILBWDATA                                0x30401F8
275 
276 #define mmTPC0_EML_CFG_DBG_AXILBWDATA_COUNT                          0x30401FC
277 
278 #define mmTPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH                     0x3040200
279 
280 #define mmTPC0_EML_CFG_DBG_AXILBWDATA_EN                             0x3040204
281 
282 #define mmTPC0_EML_CFG_DBG_D0_PC                                     0x3040208
283 
284 #define mmTPC0_EML_CFG_RTTCONFIG                                     0x3040300
285 
286 #define mmTPC0_EML_CFG_RTTPREDICATE                                  0x3040304
287 
288 #define mmTPC0_EML_CFG_RTTPREDICATE_INTV                             0x3040308
289 
290 #define mmTPC0_EML_CFG_RTTTS                                         0x304030C
291 
292 #define mmTPC0_EML_CFG_RTTTS_INTV                                    0x3040310
293 
294 #define mmTPC0_EML_CFG_DBG_INST_INSERT_0                             0x3040314
295 
296 #define mmTPC0_EML_CFG_DBG_INST_INSERT_1                             0x3040318
297 
298 #define mmTPC0_EML_CFG_DBG_INST_INSERT_2                             0x304031C
299 
300 #define mmTPC0_EML_CFG_DBG_INST_INSERT_3                             0x3040320
301 
302 #define mmTPC0_EML_CFG_DBG_INST_INSERT_4                             0x3040324
303 
304 #define mmTPC0_EML_CFG_DBG_INST_INSERT_5                             0x3040328
305 
306 #define mmTPC0_EML_CFG_DBG_INST_INSERT_6                             0x304032C
307 
308 #define mmTPC0_EML_CFG_DBG_INST_INSERT_7                             0x3040330
309 
310 #define mmTPC0_EML_CFG_DBG_INST_INSERT_CTL                           0x3040334
311 
312 #endif /* ASIC_REG_TPC0_EML_CFG_REGS_H_ */
313