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Searched refs:mmUVD_GP_SCRATCH8 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
A Duvd_6_0_d.h130 #define mmUVD_GP_SCRATCH8 0x3c0a macro
A Duvd_7_0_offset.h82 #define mmUVD_GP_SCRATCH8 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
A Dvcn_1_0_offset.h174 #define mmUVD_GP_SCRATCH8 macro
A Dvcn_2_5_offset.h649 #define mmUVD_GP_SCRATCH8 macro
A Dvcn_2_0_0_offset.h872 #define mmUVD_GP_SCRATCH8 macro
A Dvcn_3_0_0_offset.h999 #define mmUVD_GP_SCRATCH8 macro
/linux/drivers/gpu/drm/amd/amdgpu/
A Duvd_v6_0.c1080 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); in uvd_v6_0_ring_emit_vm_flush()
1095 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
A Duvd_v7_0.c1388 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); in uvd_v7_0_ring_emit_reg_wait()
A Dvcn_v1_0.c1537 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); in vcn_v1_0_dec_ring_emit_reg_wait()

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