| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | uvd_v5_0.c | 336 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_start()
378 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_start()
462 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_stop()
473 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_stop()
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| A D | uvd_v7_0.c | 869 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_sriov_start()
926 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_sriov_start()
982 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), in uvd_v7_0_start()
1033 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, in uvd_v7_0_start()
1145 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_stop()
1159 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, in uvd_v7_0_stop()
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| A D | uvd_v3_1.c | 372 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v3_1_start()
477 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v3_1_stop()
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| A D | uvd_v4_2.c | 330 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start()
435 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v4_2_stop()
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| A D | vcn_v2_5.c | 835 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
994 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start()
1346 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v2_5_stop()
1348 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v2_5_stop()
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| A D | vcn_v2_0.c | 865 UVD, 0, mmUVD_LMI_CTRL2), in vcn_v2_0_start_dpg_mode()
994 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v2_0_start()
1149 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); in vcn_v2_0_stop()
1151 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); in vcn_v2_0_stop()
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| A D | vcn_v3_0.c | 1001 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
1116 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v3_0_start()
1531 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v3_0_stop()
1533 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v3_0_stop()
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| A D | vcn_v1_0.c | 850 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v1_0_start_spg_mode()
1028 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2, in vcn_v1_0_start_dpg_mode()
1127 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), in vcn_v1_0_stop_spg_mode()
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| A D | uvd_v6_0.c | 893 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v6_0_stop()
904 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v6_0_stop()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| A D | uvd_4_0_d.h | 48 #define mmUVD_LMI_CTRL2 0x3D3D macro
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| A D | uvd_4_2_d.h | 46 #define mmUVD_LMI_CTRL2 0x3d3d macro
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| A D | uvd_3_1_d.h | 46 #define mmUVD_LMI_CTRL2 0x3d3d macro
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| A D | uvd_5_0_d.h | 52 #define mmUVD_LMI_CTRL2 0x3d3d macro
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| A D | uvd_6_0_d.h | 68 #define mmUVD_LMI_CTRL2 0x3d3d macro
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| A D | uvd_7_0_offset.h | 150 #define mmUVD_LMI_CTRL2 … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| A D | vcn_1_0_offset.h | 328 #define mmUVD_LMI_CTRL2 … macro
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| A D | vcn_2_5_offset.h | 955 #define mmUVD_LMI_CTRL2 … macro
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| A D | vcn_2_0_0_offset.h | 536 #define mmUVD_LMI_CTRL2 … macro
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| A D | vcn_3_0_0_offset.h | 1469 #define mmUVD_LMI_CTRL2 … macro
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