Searched refs:mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| A D | uvd_7_0_offset.h | 70 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| A D | vcn_1_0_offset.h | 160 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … macro
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| A D | vcn_2_5_offset.h | 869 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … macro
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| A D | vcn_2_0_0_offset.h | 824 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … macro
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| A D | vcn_3_0_0_offset.h | 1355 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | vcn_v2_0.c | 350 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
425 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_0_mc_resume_dpg_mode()
434 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1909 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_0_start_sriov()
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| A D | vcn_v2_5.c | 409 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
483 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
492 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1215 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_5_sriov_start()
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| A D | vcn_v3_0.c | 455 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
528 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
537 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1348 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v3_0_start_sriov()
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| A D | vcn_v1_0.c | 320 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
390 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_dpg_mode()
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| A D | uvd_v7_0.c | 699 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
842 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
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