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Searched refs:mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
A Duvd_7_0_offset.h74 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
A Dvcn_1_0_offset.h164 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW macro
A Dvcn_2_5_offset.h877 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW macro
A Dvcn_2_0_0_offset.h832 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW macro
A Dvcn_3_0_0_offset.h1363 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW macro
/linux/drivers/gpu/drm/amd/amdgpu/
A Dvcn_v2_5.c417 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
503 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
1229 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_5_sriov_start()
A Dvcn_v2_0.c358 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
445 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_0_mc_resume_dpg_mode()
1924 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_0_start_sriov()
A Dvcn_v3_0.c463 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
548 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
1363 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v3_0_start_sriov()
A Duvd_v7_0.c706 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
849 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
A Dvcn_v1_0.c328 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
400 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_dpg_mode()

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