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Searched refs:mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
A Duvd_5_0_d.h43 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e macro
A Duvd_6_0_d.h54 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e macro
A Duvd_7_0_offset.h106 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … macro
/linux/drivers/gpu/drm/amd/amdgpu/
A Dvcn_v2_5.c393 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
400 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
447 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
455 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
465 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
1190 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_sriov_start()
1202 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_sriov_start()
A Dvcn_v2_0.c333 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
340 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
389 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_0_mc_resume_dpg_mode()
397 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
407 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_0_mc_resume_dpg_mode()
1885 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_0_start_sriov()
1895 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_0_start_sriov()
A Dvcn_v3_0.c439 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
446 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
492 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
500 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
510 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
1323 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v3_0_start_sriov()
1334 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v3_0_start_sriov()
A Duvd_v7_0.c681 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v7_0_mc_resume()
690 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v7_0_mc_resume()
825 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in uvd_v7_0_sriov_start()
832 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in uvd_v7_0_sriov_start()
A Dvcn_v1_0.c303 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_spg_mode()
310 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_spg_mode()
371 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_dpg_mode()
380 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_dpg_mode()
A Duvd_v5_0.c284 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v5_0_mc_resume()
A Duvd_v6_0.c608 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v6_0_mc_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
A Dvcn_1_0_offset.h232 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … macro
A Dvcn_2_5_offset.h867 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … macro
A Dvcn_2_0_0_offset.h942 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … macro
A Dvcn_3_0_0_offset.h1285 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … macro

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