| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| A D | uvd_5_0_d.h | 42 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f macro
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| A D | uvd_6_0_d.h | 53 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f macro
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| A D | uvd_7_0_offset.h | 108 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | vcn_v2_5.c | 391 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
398 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
444 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
453 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
462 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
1186 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_sriov_start()
1198 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_sriov_start()
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| A D | vcn_v2_0.c | 331 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
338 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
386 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_mc_resume_dpg_mode()
395 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
404 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_mc_resume_dpg_mode()
1881 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_start_sriov()
1891 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_start_sriov()
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| A D | vcn_v3_0.c | 437 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
444 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
489 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
498 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
507 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
1320 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_start_sriov()
1331 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_start_sriov()
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| A D | uvd_v7_0.c | 677 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
688 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
822 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
830 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
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| A D | vcn_v1_0.c | 301 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
308 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
368 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_dpg_mode()
378 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_dpg_mode()
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| A D | uvd_v5_0.c | 282 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v5_0_mc_resume()
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| A D | uvd_v6_0.c | 606 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v6_0_mc_resume()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| A D | vcn_1_0_offset.h | 234 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
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| A D | vcn_2_5_offset.h | 865 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
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| A D | vcn_2_0_0_offset.h | 944 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
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| A D | vcn_3_0_0_offset.h | 1283 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
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